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What low-power features does the Cortex-M0+ architecture provide?
Arm’s Cortex-M0+ Technical Reference Manual describes integrated sleep modes, power-control optimization for system components, slower-clock operation, and optimized code fetching intended to reduce flash and ROM power. These are architectural mechanisms and design features, not a guarantee that a particular MCU will reach a specified current.
Sleep and deep sleep
| Mode | What the architecture does | What the MCU implementation determines |
|---|---|---|
| Sleep | The processor clock stops. | Which clocks, peripherals, memories and regulators continue operating, and the resulting current. |
| Deep sleep | The system clock stops. The PLL and flash memory can be switched off. The SLEEPDEEP bit selects this mode. | Whether those components actually power down, what state is retained, which wake sources remain available, and wake-up time. |
“Deep sleep” is not a single guaranteed power state across all Cortex-M0+ MCUs. A vendor may offer several levels of retention and shutdown, with different trade-offs.
Instructions and controls that enter sleep
- WFI (Wait For Interrupt): enters sleep immediately.
- WFE (Wait For Event): sleeps only when the event register is clear; it can resume when an event occurs.
- SLEEPONEXIT: returns an interrupt-driven application to sleep after an exception handler finishes, instead of returning to the interrupted thread.
These controls describe processor behavior. The MCU’s clock tree, power controller and peripherals determine which device-level resources are stopped or retained.
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How does a Cortex-M0/M0+ wake from low power?
Ordinarily, an exception must be pending at sufficient priority to wake the processor. With WFE, an event can also wake it; this can include an external event, a SEV instruction, or a pending interrupt when SEVONPEND is enabled. Which GPIOs, timers, RTCs, communication blocks or other sources can generate a usable wake event depends on the MCU and the selected power mode.
Optional wake-up hardware
Some implementations include a Wake-up Interrupt Controller (WIC). It can detect interrupts while clocks are stopped so the power-management unit can power down much of the core. That can reduce leakage, but waking through a WIC adds wake-up cycles and interrupt latency. It is optional; check the exact MCU documentation rather than assuming the feature exists.
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Microchip describes three implementation classes: normal sleep; deep sleep with WIC; and deep sleep with WIC plus state-retention power gating (SRPG), which removes power from some core sections to reduce leakage. These labels describe implementation options, not universal Cortex-M0+ modes.
Verify the complete wake path
- Check the MCU reference manual for wake-capable sources in each specific power mode, and the datasheet for their current and timing conditions.
- Measure the full transition, including oscillator startup and any peripheral reinitialization, against the application’s latency limit.
- Test for unexpected debug or event wake-ups. Arm notes that software may need to re-enter sleep after such an event.
How much current does a Cortex-M0/M0+ use?
The core architecture does not prescribe one current figure. STMicroelectronics gives a 5–50 µW/MHz range for core dynamic power on its current Cortex-M0+ page, but explicitly cautions that the core alone does not represent a device’s overall power consumption. MCU figures also depend on voltage, frequency, memory retention, enabled peripherals, regulator behavior, I/O and board leakage, among other conditions.
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The vendor examples below illustrate the spread of device-level figures; they are not Cortex-M0/M0+ limits and are not directly interchangeable. The cited product-page summaries do not provide all test conditions for every figure, so consult the relevant datasheet before using one as a design target.
| Device and vendor source | Reported state or metric | Reported figure and qualification |
|---|---|---|
| TI MSPM0G3105, Texas Instruments 2026 product page | RUN | 101 µA/MHz, CoreMark. |
| TI MSPM0G3105, Texas Instruments 2026 product page | SLEEP | 40 µA/MHz. |
| TI MSPM0G3105, Texas Instruments 2026 product page | STOP | 190 µA at 4 MHz. |
| TI MSPM0G3105, Texas Instruments 2026 product page | STANDBY | 1.5 µA with a 32 kHz LFXT, RTC, SRAM, CPU state and registers retained. |
| TI MSPM0G3105, Texas Instruments 2026 product page | SHUTDOWN | 80 nA with I/O retained and I/O wake-up. |
| NXP MCX C04x, NXP Semiconductors 2026 product page | Static power | 2.2 µA; further conditions are not stated in the cited product-page summary. |
| NXP MCX C04x, NXP Semiconductors 2026 product page | Deep-sleep static power | 77 nA; further conditions are not stated in the cited product-page summary. |
| NXP MCX C04x, NXP Semiconductors 2026 product page | Full-retention wake-up | 7.5 µs; the cited product-page summary does not state further timing conditions. |
The TI MSPM0G3105 product page specifies a 1.62–3.6 V supply range and operation up to 80 MHz. The NXP MCX C04x page identifies a 48 MHz Cortex-M0+ core. Those device specifications do not make the listed power figures comparable under identical test conditions.
Power and current are different quantities: a core dynamic-power figure in µW/MHz cannot be treated as a current figure in µA/MHz without the operating voltage and the measurement conditions. For battery life, use the MCU’s mode-specific current data together with measured board current and the actual time spent in each mode.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What should a low-power requirement specify?
Define acceptance criteria for the complete MCU and board. A peak-current target alone can be misleading: a mode with very low sleep current may consume more energy overall if it increases wake latency, requires more active work, or cannot preserve the needed state.
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- Energy budget and duty cycle: set budgets for run, idle, sleep, deep sleep and transitions between them. Include how often the device wakes and how long it stays active, not just peak current.
- Latency and wake sources: specify the maximum acceptable wake-up time and identify which interrupts, GPIOs, timers, RTCs, DMA engines or communication peripherals must remain wake-capable.
- Retention: say whether flash, SRAM, CPU registers, peripheral state and debug logic must retain state. Their retention choices have different current consequences.
- Clock policy: compare energy per completed task. A higher clock may finish active work sooner; a lower clock may reduce instantaneous dynamic power. Verify the result on the chosen silicon.
- Board-level losses: account for unused peripherals, regulator quiescent current, I/O pull resistors, analog references, oscillator startup, board leakage and debug probes.
- Test conditions: state voltage and temperature corners and the clocks, memories, peripherals and regulators used for measurement. Vendor current figures are meaningful only in their stated configuration.
How should two Cortex-M0/M0+ MCUs be compared?
Compare them in the conditions your product needs, rather than ranking them by a single shutdown-current number.
- Active energy per completed task, as well as active current.
- Sleep and deep-sleep current at the intended voltage, clock and temperature.
- Which state is retained, including SRAM, flash, CPU state and peripheral state.
- Wake-up latency and the sources that remain available in each mode.
- Oscillator-startup and regulator losses, including supply-voltage range.
- Memory-retention behavior, package and peripheral leakage, and debug/tool effects.
A lower headline shutdown current is useful only if the associated wake latency, state retention and available wake sources still meet the application’s requirements.
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