In a 2020 interview, RISC-V CTO Mark Himelstein argued that the open instruction set’s success would depend not just on the ISA, but on the software, tools, hardware and industry support needed to turn it into deployed products. He outlined where adoption could move first—and why broad computing systems would take longer.
Who was Mark Himelstein, and what shaped his RISC-V role?
In an interview with EE Times published August 7, 2020, Himelstein brought experience across instruction-set architecture (ISA) design, compilers, operating systems and large-scale systems. He said he was MIPS employee number 45, working on compilers, optimizers, operating systems and ISA design. He later ran Solaris at Sun Microsystems for five years and founded Graphite Systems, where he was CTO before EMC acquired the company in 2015.
Himelstein said former MIPS colleagues proposed him for the RISC-V CTO role. He accepted because both the technical challenge and the people involved appealed to him. His description of the role joined technical planning with practical adoption: completing specifications, identifying what applications need, and explaining the technology publicly.
What did the CTO do?
Himelstein described three strands of responsibility, all aimed at connecting the architecture to usable products:
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- Flexible MCU Board: Incorporate the ESP32-C3 32-bit RISC-V chip, operating up to 160 MHz, mounted multiple development ports,
- Developer Friendly: Compatible with Arduino IDE, MicroPython, CircuitPython, PlatformIO, ESP IDF, Zephyr, Matter, ESPNow, Meshtastic, WLED, ESPHome, Home Assistant, Ubidots
- Outstanding RF performance: Complete Wi-Fi functions and Bluetooth Low Energy, while supporting communication over 100m with anFL antenna
- Elaborate Power Design: 4 working modes as low as 44 μA in deep sleep mode, while supporting lithium battery charge management
- Thumb-sized Design: 21 x 17.5mm, Seeed Studio XIAO series classic form factor
- Move specifications forward. Coordinate specification work and analyze gaps between what the architecture offered and what applications required.
- Plan with industry verticals. Work with sectors such as automotive and cloud computing to ensure their requirements were covered, rather than treating the ISA as an end in itself.
- Explain and promote the work. Speak with media, attend conferences and help potential adopters understand the technology.
He saw the CTO as a bridge between ISA design and applications—someone who could make hardware and software teams work through their requirements together. He put the job’s priority plainly: “My number one goal is the deployment of products with real RISC-V cores. In the end, that’s the only thing that counts.” That was his stated goal in the 2020 interview, not a measure of adoption achieved since then.
Why did he think RISC-V could matter?
Himelstein’s case rested on two related ideas: an open development model and an extensible ISA. He called RISC-V “the first open source chip of this magnitude that started as open source.” His comparison was to Linux: an open technology could become commonplace when users valued not being dependent on the control of one large entity.
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He also argued that the design community could draw on experience accumulated across MIPS, SPARC, Arm and x86. In his view, RISC-V’s extension model could serve very different workloads, from small Internet of Things (IoT) devices and edge networks to cloud servers and supercomputers. This was an argument about architectural flexibility and opportunity—not evidence that the same RISC-V implementation would suit every workload, or that performance or market adoption had already been established.
Why was the ecosystem as important as the ISA?
A processor architecture is only useful to adopters when the surrounding components work with it. Himelstein emphasized software, compilers, tools, cores and development boards alongside the ISA itself. He identified practical ecosystem work including boot loaders, configuration files, Linux ports, compilers and security guidance.
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- The ESP32-C3 SUPERMINI is positioned as a high-performance, low-power, cost-effective IoT mini development board, suitable for low-power IoT applications and wireless wearable applications
- It is equipped with a rich set of interfaces, including 11 digital I/Os that can be used as PWM pins and 4 analog I/Os that can be used as ADC pins.
- It supports four serial interfaces, including UART, I2C, and SPI.
- The ESP32-C3 features a 32-bit RISC-V CPU, including an FPU (Floating Point Unit) capable of 32-bit single-precision
- Package: 2PCS ESP32-C3 MINI Development Board ESP32 SuperMini ESP32 C3 WiFi Module
RISC-V International was also developing profiles and conducting gap analysis, he said. The aim was to give users clearer expectations about application compatibility and guidance suited to particular workloads. Profiles and gap analysis matter because a general ISA alone does not tell a buyer whether a particular software stack, system configuration or application will be ready.
Himelstein pointed to collaboration with OpenHW Group, CHIPS Alliance and OpenTitan. He also highlighted the need for user stories: adopters should be able to say who uses the technology, why they use it and what benefit it brings. In the interview, he cited approximately 600 RISC-V members and approximately 120 organizations developing cores and hardware, figures reported for 2020. Those counts describe the community at that time; they are not current membership figures or a measure of commercial deployment.
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- ESP32-C6 WiFi 6 microcontroller development board adopts ESP32-C6-WROOM-1-N8 module, which is equipped with RISC-V 32-bit single-core processor, up to 160MHz main frequency, built-in 8MB Flash
- Integrates WiFi 6, Bluetooth 5 and and IEEE 802.15.4 (Zigbee 3.0 and Thread) wireless communication, with superior RF performance
- Integrates rich peripherals including SPI, UART, I2C, I2S, LED PWM, SDIO and other interfaces, compatible with the pinout of ESP32-C6-DevKitC-1-N8 development board, more convenient to use and expand a variety of peripheral modules
- Onboard CH343 and CH334 USB HUB chips, supports USB and UART development at the same time via a USB-C port
- Comes with online examples and tutorials for ESP-IDF development environment
What slowed RISC-V hardware adoption?
Himelstein’s central caution was that silicon and software do not move on the same schedule. Software can often be developed and updated more quickly, while a hardware product must pass through prototypes, customer trials, iterations and production planning. A late change to a chip can therefore affect a long product schedule.
He said broad enterprise computers—especially multiprocessor and multisocket systems—needed a larger ecosystem. Such systems depend on many software components and tools working together, which makes readiness more demanding than for an application with a narrower initial scope. In contrast, he saw IoT, cloud-server and high-performance computing (HPC) applications as possible earlier opportunities because their initial application lists could be more limited.
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- Ample PSRAM Storage – The development board offers 8MB PSRAM, providing substantial extra memory for handling more complex tasks, large data buffers, and advanced processing.
- Enhanced Multi-Tasking Capability – With the additional 8MB PSRAM, the ESP32-C5-WIFI6-KIT can efficiently manage multiple protocol stacks simultaneously, ensuring smooth operation in multi-tasking IoT environments.
- Support for Medium-Load Applications – The 8MB PSRAM allows the ESP32-C5 to handle medium-load applications more effectively, making it ideal for scenarios requiring real-time data processing or continuous communication.
- Seamless Performance – The increased memory improves the overall performance and responsiveness of the device, particularly when running applications with larger memory footprints or more demanding computations.
- Future-Proof for Complex Projects – With 8MB of PSRAM, developers are better equipped to build scalable, high-performance solutions that support both current and future IoT use cases, offering flexibility for future-proofing designs.
Automotive added another timing constraint: Himelstein described product cycles of approximately five years. That is his 2020 characterization of the sector’s cycle, not a universal duration for every automotive program. It illustrates why automotive adoption requires early planning and why a promising architecture can take years to appear in a production vehicle.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Which industries did he prioritize?
Himelstein named four near-term focus areas: IoT, automotive, HPC and cloud servers. His reasoning was that these fields offered more focused entry points than general-purpose computing, which needed broader ecosystem support. The table distinguishes what the interview directly said from the practical implications of that reasoning.
| Area | What Himelstein said in 2020 | Adoption consideration |
|---|---|---|
| IoT | A priority area with a potentially narrower initial application list. | A focused use case may need fewer components ready at first than broad enterprise computing; the interview gives no specific product schedule. |
| Automotive | A priority area; he cited product cycles of approximately five years. | Long development cycles make early ecosystem and requirements planning important. |
| HPC | A priority area that could move sooner where initial applications are narrower. | Workload-specific gaps and software readiness remain relevant; the interview does not give performance benchmarks. |
| Cloud servers | A priority area that could move sooner where initial applications are narrower. | Specific deployments may have a more bounded initial scope than general-purpose enterprise systems; no deployment counts were given. |
These priorities were a CTO’s roadmap emphasis in 2020, not a ranking of current RISC-V adoption. Himelstein offered no market-share figures, revenue forecast, adoption percentage or performance benchmark in the interview.
What did the interview say about RISC-V’s international structure?
Himelstein said Switzerland was chosen as the legal entity’s neutral location to give members comfort about potential geopolitical exposure. He described the organization’s operations and participation as global. This is his explanation from 2020; it does not establish current export-control obligations or guarantee that a particular product, company or transaction faces no geopolitical restrictions.
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Himelstein identified development boards as part of the infrastructure needed to make the ecosystem usable. A board can give developers a physical platform to experiment with a RISC-V core and its software stack. The interview does not name a board model, provide specifications or establish present-day availability, so a buyer should check current board documentation and regional stock rather than infer a recommendation from the 2020 discussion.
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