Cadence announced Cobra on June 9, 1997, as a cycle-based simulator for speeding long digital-design regressions. It was designed to work alongside—not replace—Cadence’s event-driven NC-Verilog simulator: engineers could run long simulations in Cobra, then use NC-Verilog when they needed detailed event-level debugging. Cadence advertised a 30–100× speed advantage over event-driven simulators, but that was a launch claim, not an independently verified benchmark.
What Cadence announced in 1997
Cadence publicly debuted Cobra at the 34th Design Automation Conference in Anaheim on June 9, 1997. The simulator was part of a broader system-chip verification strategy aimed at designs whose size and complexity made conventional simulation runs difficult to complete quickly.
Cadence said Cobra was in production use at customer sites after an 18-month test period with technology partners, as reported by EE Times in 1997. The announcement described a tool for large digital systems, including multimillion-gate designs, rather than a general-purpose replacement for every stage of chip verification.
How cycle-based simulation differed from event-driven simulation
| Aspect | Cobra cycle-based simulation | NC-Verilog event-driven simulation |
|---|---|---|
| How simulation advances | Advances and reports logic state at clock-cycle boundaries. | Evaluates changes as they occur, including activity between clock boundaries. |
| Best fit in the announced workflow | Long synchronous regressions where throughput matters. | Detailed checks and debugging where event-level behavior matters. |
| Trade-off | Designed for speed on large designs, with less event-level detail. | Provides finer timing and activity detail, but can be slower on long runs. |
The practical idea was to use both tools for different jobs. A team could use NC-Verilog for detailed checks such as initialization and debugging, then use Cobra to run longer regressions. Cadence positioned this combined workflow as a way to balance simulation detail against the need to process large designs efficiently.
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How Cobra’s engine was intended to improve throughput
Cobra used multi-valued decision diagram (MDD) technology developed at Cadence Berkeley Labs. In the company’s description, the approach represented Boolean logic as decision trees and used lookup tables—multiple decision diagrams—to replace combinatorial logic evaluation. The goal was to increase simulation throughput for very large designs.
The launch materials claimed runtimes 30–100 times faster than event-driven simulators such as Verilog-XL. That range is a contemporaneous Cadence product claim; the available historical reporting does not provide an independent benchmark or enough test conditions to treat it as a guaranteed speedup for a particular design.
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Target applications and model types
Cadence named video, network switching, image processing and microprocessor design among the intended applications. Cobra was described as supporting mixed behavioral, RTL and gate-level designs, and more than a synthesizable-only Verilog subset. The broader system-chip strategy also involved reusable IP views, instruction-set models, and high-speed bus-functional or cycle-accurate models.
HDL and integration support
At launch, Cobra supported Verilog HDL. Cadence planned VHDL integration for 1998; the announcement therefore establishes a plan, not proof that the feature shipped on that schedule. OMI and PLI 1.0/2.0 support were intended to connect system-level tools and HDL-based tools, link system models, and support external models and control.
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Cobra was one element of a larger verification approach. Cadence also described coverage analysis and a Quickturn hardware-emulation partnership as complementary parts of that strategy. These broader elements should not be confused with Cobra’s cycle-based simulation engine itself.
Launch plans, platforms and price
Cadence planned volume shipments for December 1997 on Sun Solaris and Hewlett-Packard Unix workstations. The announced US$60,000 price was a floating-license list price at launch, not evidence of a current price or present-day availability.
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The same 1997 report placed the announcement within Cadence’s broader verification business: it cited 25,000 worldwide Verilog installations for Cadence’s verification solution and said 1,100 NC-Verilog licenses were in production at more than 160 companies. Those figures describe the reported 1997 context, not Cobra sales or current market use.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What happened to Cobra after launch
A 1998 EE Times report placed Cobra in Cadence’s Affirma co-execution family and cited a US$20,000 Cobra co-execution option. That is a historical product-family and pricing reference; it does not establish that Cobra is sold or supported today.
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The available historical record establishes Cobra’s 1997 launch plan and its later appearance in Affirma, but not its availability in 2026. It also does not establish a current download, license, support path, or compatibility with Cadence Xcelium. Readers looking for a present-day simulator should confirm product status and support directly with Cadence rather than infer continuity from the historical name.
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