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An SPD EEPROM is the small nonvolatile memory chip on a RAM module that records the module’s identification and configuration data. When a computer starts, motherboard firmware reads that record over a two-wire serial bus and uses it to configure memory. If you need to replace one on a DDR4 DIMM, match the DDR4-specific SPD device standard, not just the chip’s capacity or its resemblance to a familiar 24-series EEPROM.
What an SPD EEPROM does
SPD stands for Serial Presence Detect. The EEPROM stores a module’s standardized identification and configuration information so system firmware can determine how to initialize the installed memory. It is a record on the DIMM, not the memory cells that hold programs and files while the computer is running.
For DDR4, onsemi describes its N34C04 as a 4-Kbit EEPROM implementing the JEDEC JC42.4 (EE1004-v) SPD specification. Its datasheet, published in September 2024, identifies support for standard-mode 100 kHz, fast-mode 400 kHz, and fast-plus 1 MHz I²C operation. These are supported bus rates for that device, not a claim that every motherboard uses each rate.
How the motherboard reads the SPD
The SPD device communicates over a two-wire serial interface: SCL carries the clock and SDA carries bidirectional data. The motherboard’s I²C master controller initiates communication. On a multi-slot design, the clock and data lines can be shared, while address pins identify the device associated with a slot.
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STMicroelectronics’ M34E04B documentation shows SA0, SA1, and SA2 wired to encode module addresses. That arrangement provides up to eight slot addresses in the illustrated scheme. The exact wiring and address use depend on the board design; the figure is not a guarantee that every system implements eight populated slots.
How DDR4 SPD memory is organized
The N34C04 provides 4 Kbits of storage arranged as two 2-Kbit banks. One bank is active at power-up, and software commands select the bank. The device also divides storage into four 1-Kbit blocks, each of which can be write-protected through software. Its feature list specifies a 16-byte page-write buffer.
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It also specifies hardware write protection for the entire memory. As a result, writing SPD data is not simply a matter of connecting a programmer: the board’s wiring, device protection state, bank selection, and programming method all matter. A replacement or reprogramming attempt should preserve valid SPD contents, including any required CRC fields; invalid or inconsistent data can prevent correct memory initialization.
Is an EE1004 the same as a 24C02?
No. EE1004-v is the DDR4 SPD device specification implemented by parts such as the onsemi N34C04. A chip described generically as a 24C02 belongs to a different EEPROM family and should not be assumed compatible just because both devices use a serial interface or have a similar package.
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- Built-in pull-up resistor required for I2C communication;
- All pins lead out and are marked, the address input and the direct jumper settings for the write protect pin;
- PCB size: 36.5 x 12 x 12 mm (L x W x H)
Generation matters, too. DDR5 uses a separate SPD contents standard and may use a different type of SPD device. A DDR4 EE1004-compatible part and a DDR5 SPD hub are not interchangeable by name alone. Confirm the memory generation and exact device requirements before selecting a replacement.
What to check before replacing a DDR4 SPD EEPROM
Identify the installed memory generation and module type, then verify each electrical and functional requirement against the module or board design and the candidate’s datasheet. For example, the onsemi N34C04 specifies a 1.7–3.6 V supply range; that range is specific to this part, not a universal SPD voltage specification.
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- JEDEC device family: Confirm that the replacement supports the DDR4 EE1004-v SPD requirements; do not select by capacity or “24-series” wording alone.
- Package and pinout: Match the physical package and signal positions to the DIMM’s footprint.
- Supply voltage and bus: Check that the device’s operating voltage and SMBus/I²C behavior are suitable for the board, including relevant speed support.
- Addressing: Confirm address-pin requirements and how the DIMM or motherboard wires them.
- Organization and protection: Check bank selection, page-write behavior, and hardware and software write-protection controls.
- Data and programming path: Ensure you have valid SPD data for the module and a safe, compatible way to program it. A blank chip is not a usable substitute for correctly programmed module data.
Which DDR4 SPD EEPROM should you choose?
The N34C04 from onsemi and M34E04B from STMicroelectronics are documented component options associated with EE1004-compatible DDR4 SPD designs. They are chips, not complete RAM-module recommendations. Choose between them only after comparing the actual part datasheets against the DIMM’s requirements.
| Check | What the cited device documentation establishes |
|---|---|
| onsemi N34C04 | 4-Kbit EE1004-v DDR4 SPD EEPROM; 1.7–3.6 V supply range; 100 kHz, 400 kHz, and 1 MHz I²C speed classes; two 2-Kbit banks; four software-protectable 1-Kbit blocks; whole-memory hardware write protection; 16-byte page-write buffer. Source: onsemi N34C04 datasheet. |
| ST M34E04B | Documented as a DDR4 SPD component; its module-addressing figure shows shared clock and data lines and SA0/SA1/SA2 slot-address wiring. Check the datasheet for the exact package, voltage, operating limits, and protection behavior of the specific part. Source: ST M34E04B datasheet. |
The table does not establish that either part is a drop-in replacement for every DDR4 DIMM. Verify the exact ordering code and datasheet details, the board’s address and protection wiring, and the availability of a compatible programmed image before buying or attempting a repair.
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Sources and generation context
- onsemi N34C04 datasheet, September 2024, for EE1004-v compliance, capacity, electrical range, bus speeds, organization, and write protection.
- STMicroelectronics M34E04B datasheet, for the shared-bus and slot-addressing illustration.
DDR5 has a separate JEDEC SPD contents standard; the cited DDR4 component details should not be applied to DDR5 devices.
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