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Intel’s September 16, 2002 announcement described a communications-focused branch of its 90-nm manufacturing platform—not a claim that every 90-nm Intel chip used the same SiGe devices. The branch combined the platform’s strained-silicon CMOS foundation with silicon-germanium heterojunction bipolar transistors and mixed-signal components for broadband, optical, wireless, and personal-area-network equipment.

What Intel announced

At the Intel Developer Forum on September 12, 2002, Intel disclosed that it would include SiGe in a communications version of its 90-nm platform. The company formally announced that process on September 16, targeting communications products for introduction in 2003. Intel executive Sean Maloney said the combination of mixed-signal circuitry, SiGe, and advanced CMOS manufacturing would bring Moore’s Law benefits to communications silicon.

EE Times reported that Intel planned to manufacture the communications chips in its own 300-mm wafer fabs in the 2003 time frame. The publication also identified a 40-Gb/s SerDes device and a wideband-CDMA chip as test vehicles. Those reports describe plans and development vehicles at the time; they do not establish eventual production volume or commercial success.

How the communications process differed from base 90-nm logic

The communications process shared a manufacturing foundation with Intel’s 90-nm logic generation, but added devices and components aimed at mixed-signal and radio-frequency work. The distinction matters: Intel announced a communications-specific branch, not a single SiGe device stack for every product made on the 90-nm generation.

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#1 Best Overall
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  • Communication Integrated Circuits
  • 5piece SE2576L-R SIGE 2576L SE2576L QFN-16 Chipset
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Aspect 90-nm logic foundation Communications-focused variant
Intended use General-purpose logic; Intel identified Prescott as the first general 90-nm product generation. Broadband, optical, wireless, and personal-area-network equipment, as described in Intel’s September 16, 2002 announcement.
Core manufacturing Strained-silicon CMOS, seven copper interconnect layers, low-k dielectric, and 300-mm wafers, according to Intel’s 2002 process description. Built on the 90-nm platform and specified for 300-mm wafers, with communications-specific device and circuit additions.
Transistor and circuit mix CMOS logic transistors. CMOS plus SiGe heterojunction bipolar transistors, RF analog CMOS, and precision passive components.
Integrated components The August 2002 process description highlighted a one-square-micron SRAM cell; it did not specify the communications-specific RF components listed at right. Intel described precision passives, inductors, and varactors alongside the transistor technologies.
Performance emphasis Logic-process scaling and SRAM integration. High-speed communications: Intel associated its SiGe transistors with data rates of 50 Gb/s and higher.
Product schedule Prescott was identified as the first general 90-nm product generation. Intel targeted communications product introductions in 2003; EE Times reported 2003 as the planned manufacturing time frame.

Two different roles for SiGe

Embedded SiGe as part of strained CMOS

Intel’s later technical reference explains that the 90-nm generation introduced strain for both NMOS and PMOS transistors. For PMOS, Intel replaced conventional source/drain material with strained SiGe, commonly called embedded SiGe or e-SiGe. For NMOS, it used a high-stress layer. Intel said these strain techniques increased channel mobility and drive current. This is a transistor-engineering technique within the CMOS generation.

SiGe bipolar transistors for communications

The communications variant also added SiGe heterojunction bipolar transistors (HBTs). These are not the same thing as the embedded SiGe used to strain PMOS source/drain regions: they are a distinct transistor type added to the communications device mix. Intel paired them with RF analog CMOS and passive components to support communications circuits that combine digital processing with analog and high-frequency functions.

Why add devices beyond ordinary CMOS?

Communications equipment has to process signals as well as digital data. A process that combines CMOS logic with RF analog circuitry, high-speed SiGe HBTs, and components such as inductors and varactors can bring more of those functions into one manufacturing platform. Intel’s stated target of 50 Gb/s and higher for the SiGe transistors indicates the speed class it was addressing; it is not a claim that every chip made in the process operated at those rates.

The announcement presented integration as a way to apply Intel’s advanced manufacturing platform to communications silicon. It did not, by itself, demonstrate how much of the system could be consolidated into a finished product or establish the process’s later market results.

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What the 2002 demonstrations showed

Intel’s August 13, 2002 account of the 90-nm logic process reported a functional 52-megabit SRAM demonstration with one-square-micron SRAM cells. Intel also reported 330 million transistors for the 90-nm Prescott-related SRAM/process demonstration; period reporting cited the same count in the context of the first 90-nm Pentium 4 product. These are demonstrations and product-context figures reported by Intel in 2002, not measurements of the communications process’s eventual commercial output.

How the announcement fit the timeline

Date What Intel or contemporaneous reporting said
August 13, 2002 Intel described the 90-nm logic process, including strained silicon, copper interconnects, low-k dielectric, 300-mm wafers, and SRAM demonstrations.
September 12, 2002 At the Intel Developer Forum, Intel disclosed that SiGe would be included in a communications version of the 90-nm platform.
September 16, 2002 Intel announced the communications-process capabilities and targeted product introductions in 2003.
2003 target Intel planned communications chips on the process; Prescott was identified as the first general 90-nm product generation.

What the announcement does—and does not—establish

Intel’s 2002 statements establish what the company planned and how it described the process: a common 90-nm CMOS foundation, with a communications branch adding SiGe HBTs and mixed-signal features. They do not establish the branch’s eventual production volume, market share, or financial outcome. The 40-Gb/s SerDes and wideband-CDMA chip were reported as test vehicles, while 50 Gb/s and higher was Intel’s stated data-rate class for its SiGe communications transistors.

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