To reduce power in a Cypress PSoC, first disable unused clocks, peripherals and analog blocks, then select the lowest power mode that still preserves the memory, clocks, peripherals and wake sources your application needs. The right mode depends on the exact PSoC part: PSoC 4 and PSoC 6 differ, and devices within each family do not necessarily support the same modes or retain the same resources.
Choose a mode from what must keep working
Before changing firmware, list the resources the device must preserve while idle: CPU activity, SRAM contents, timing sources, peripheral operation, GPIO state and the events that must wake the system. Then check the exact part’s datasheet and technical reference manual (TRM). Mode names alone do not guarantee identical behavior across PSoC subfamilies.
- Short idle intervals: use a sleep state that stops CPU execution but leaves needed system resources available.
- Longer idle intervals: consider deep sleep if the application can tolerate the loss of high-speed clocks and peripherals not supported in that mode.
- Minimum-retention designs: consider hibernate or another lowest-power state only after confirming what state and wake capability the part preserves.
Power modes are only one part of the budget. Gating unused resources in Active mode and reducing the time the CPU spends awake can matter as much as choosing a deeper state.
How PSoC 4 sleep modes differ
Infineon’s AN86233 describes up to five PSoC 4 power modes, but not every PSoC 4 device implements all five. Verify the mode names and resource behavior for your specific part rather than assuming a family-wide feature set.
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| Mode | CPU and clocks | Resources and wake behavior |
|---|---|---|
| Sleep | The CPU clock stops. | Peripherals remain available; an enabled interrupt can wake the CPU. Exact resource behavior is device-dependent (Infineon AN86233 and the device TRM). |
| Deep Sleep | High-speed logic and the IMO are disabled. | Low-frequency clocks and selected low-power or asynchronous peripherals remain available. Supported wake sources depend on the device (Infineon AN86233 and the device TRM). |
| Hibernate or Stop, where supported | Lower-power behavior comes with trade-offs in retention and wake capability. | Retention and wake options are part-specific; consult the device datasheet (Infineon AN86233). |
Enter Sleep or Deep Sleep
- Inventory the peripherals, SRAM contents, clock accuracy and wake events the application requires.
- Disable unused peripherals and clock sources, and gate unused regulators or blocks where the device and firmware flow allow it. The PSoC 4 TRM identifies peripheral, regulator, clock and block gating as key power controls.
- For a short idle period, enter Sleep after configuring the interrupts that should wake the CPU. Sleep stops CPU execution while peripherals can remain available.
- For a longer idle period, configure a supported wake source and enter Deep Sleep. The device may retain low-frequency clocks and selected low-power or asynchronous peripherals, but not high-speed logic or the IMO.
- Use Hibernate or Stop only if the exact part supports the mode and its retention and wake limitations fit the application.
Potential PSoC 4 wake sources include GPIO, watchdog and low-power comparator events, but availability and configuration vary by device. Confirm the supported sources in the relevant device documentation before relying on one.
Which PSoC 6 power mode to use
PSoC 6 separates system-level power modes from CPU-level modes. System modes include LP, ULP, Deep Sleep and Hibernate; each CPU also has Active, Sleep and Deep Sleep states. This distinction matters: putting a CPU to sleep is not the same operation as putting the whole system into Deep Sleep.
| State | CPU execution | Retention and available resources | Wake considerations |
|---|---|---|---|
| CPU Sleep | The CPU stops executing code. | System resources can remain available. | Use when code can pause but the system still needs active resources; select interrupts or events appropriate to the device. |
| System Deep Sleep | Both CPUs must request the transition; CPUs then turn off. | Most peripherals and high-frequency clocks turn off. Low-frequency clocks, selected low-power analog and digital peripherals, and SRAM retention remain. | Wake options depend on the retained resources and the device’s supported sources. |
| System Hibernate | CPUs are off. | Clocks are off, GPIO outputs are frozen, and SRAM is not retained. | Wake options are limited to supported comparator, RTC, dedicated-pin and backup-domain functions. |
Infineon’s AN219528 says PSoC 6 gains the best power-saving benefit when low-power modes are used alongside other power-saving techniques without significantly sacrificing performance. In practice, keep active bursts short and sleep intervals long where the workload allows it.
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Configure PSoC 6 low-power behavior
- In ModusToolbox, use the Low-Power Assistant (LPA) to configure power resources, core regulators, VBACKUP behavior and wake pins. The available settings depend on the device and project.
- If using the LPA’s RTOS flow, configure the lowest automatic mode in the RTOS section, consistent with the resources and wake events the application needs.
- Start with CPU Sleep for idle periods that must leave system resources available.
- Request system Deep Sleep only when both CPUs can enter it and the application can operate with the resources retained in that state.
- Choose Hibernate only when loss of SRAM and the narrower wake-source set are acceptable.
- For runtime transitions or power settings beyond static configurator setup, use the device-supported HAL or SysPm APIs.
Keep sensing active without waking the CPU
Some PSoC 6 designs can collect periodic sensor measurements during system Deep Sleep. For example, the CY8C62x4 family can operate required analog resources such as op-amps, an ADC, a DAC and a reference while the CPU and other peripherals are powered off. That can avoid waking the CPU for every conversion.
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This pattern is not a blanket promise that every channel or sampling schedule will work in Deep Sleep. Check the exact device’s channel, sample-rate, reference and duty-cycle limits, then confirm that the required analog blocks are available in the selected state.
Reduce power before and after entering a low-power state
- Gate what is unused: disable idle peripherals, clock sources and analog blocks; use the device’s supported clock, regulator and block controls.
- Minimize awake time: batch work into short active periods where the workload permits it, then sleep for longer intervals.
- Review the whole board: LEDs, pull-ups, attached sensors, external regulators and debug probes can draw current even when the PSoC is in a low-power mode.
- Use only necessary wake sources: configure the events the application actually needs, and verify they remain available in the chosen mode.
Measure the assembled design, not just the mode name
Infineon’s AN219528 gives illustrative PSoC 6 figures under example CY8C61x6 datasheet conditions: 1.7 mA for CM4 Active, 0.76 mA for CM4 Sleep and 7 µA for system Deep Sleep. These are condition-specific reference figures, not guaranteed consumption for every PSoC 6, board or firmware configuration. Use the exact part’s documentation and measure your own design.
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- Measure Active, entry, steady-state low-power, wake and duty-cycled average current on the assembled hardware.
- Keep supply voltage and clock configuration consistent when comparing states; disconnect the debugger where appropriate.
- Check for unintended current paths through sensors, pull-ups, LEDs, debug hardware and external regulators.
- Record the part number and datasheet revision, supply voltage, temperature, clock configuration, firmware build and instrument settings with each result.
Tools and hardware to check
Infineon recommends ModusToolbox for many PSoC 4 devices covered by AN86233; PSoC Creator supports a subset of devices. Confirm that the selected tool and its version support the exact part and power-mode workflow in your project. PSoC 6 hardware design also requires attention to package, power rails, clocking, reset and I/O configuration.
Infineon lists the CY8CKIT-040 PSoC 4000 Pioneer Kit in its PSoC 4000 family documentation as a prototyping option. Check the silicon revision and tool support for the intended work before selecting a kit.
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