Do these 3 things before closing this tab:
1Clear out junk files and repair common Windows errors2Fix the driver behind crashes, sound loss and screen glitches3Repair Windows errors before they cause bigger problemsProbably—but it is a plausible industry roadmap, not a guarantee. imec forecast that Moore’s Law could continue for another 8 to 10 years in a semiconductor-trends article published around 2020. In 2026, ASML and TSMC are still laying out steps toward High-NA EUV manufacturing, including a planned TSMC start in 2030. Whether those milestones translate into affordable, high-yield chips depends on more than a scanner’s resolution.
What EUV has to do with Moore’s Law
Moore’s Law is the long-running observation that the number of transistors that can be economically integrated on a chip tends to increase over time. It is not a physical law requiring transistor counts to double on a fixed schedule. The pace depends on whether chipmakers can make denser designs practical to manufacture and sell.
Extreme ultraviolet (EUV) lithography uses very short-wavelength light to pattern features on silicon. Compared with older patterning approaches, EUV can make some advanced structures with fewer patterning steps. That can help chipmakers continue scaling, but the result depends on the chip design, manufacturing process, yield, power and performance—not simply the lithography tool.
High-NA EUV is the next generation of the platform. ASML’s product information gives its numerical aperture as 0.55, up from 0.33 for conventional EUV. The higher numerical aperture is intended to improve optical resolution, allowing finer patterns. ASML says it has invested €6 billion in EUV research and development over 17 years; that figure describes its investment, not a guarantee of future cost or manufacturing performance.
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What changes with High-NA EUV?
The higher-NA optics are only one part of the transition. High-NA also affects exposure fields, mask handling and stitching, and puts demands on process control and the surrounding manufacturing ecosystem. The available company statements describe the direction of travel, but do not give comparable numerical specifications for every production trade-off.
| Area | Conventional EUV, 0.33 NA | High-NA EUV, 0.55 NA |
|---|---|---|
| Numerical aperture and intended resolution | 0.33 NA (ASML product information) | 0.55 NA; designed to improve optical resolution for finer patterning (ASML product information) |
| Patterning steps | EUV can reduce the number of patterning steps compared with older approaches; a specific conventional-EUV count is not stated (ASML product information) | A specific step count or reduction is not stated (ASML product information) |
| Scanner productivity | A comparable productivity figure is not stated (ASML product information) | ASML says 12-inch masks can support greater scanner productivity; it does not provide a comparable numerical figure in the cited statements (ASML and TSMC, 2026) |
| Mask format | Current 6-inch masks are part of ASML’s stated adoption sequence (ASML and TSMC, 2026) | A 12-inch photomask pilot line is targeted for 2031 (ASML and TSMC, 2026) |
| Exposure fields and stitching | A directly comparable field or stitching specification is not stated (ASML product information) | High-NA changes exposure-field and stitching constraints; specific dimensions or limits are not stated (ASML product information) |
| Resists, pellicles, tool cost and yield | Comparable values are not stated in the cited company statements | Manufacturing readiness depends on suitable materials, cost and yield learning; comparable values are not stated in the cited company statements |
| Ecosystem maturity | A maturity comparison is not stated | Intel and ASML are working on standards, infrastructure, materials and supplier readiness (Intel Foundry, 2026) |
In other words, higher resolution is an enabling capability, not a finished manufacturing recipe. Chipmakers have to establish workable masks and materials, control the process, and reach yields and throughput that make production viable.
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- The original value of un-polished wafer is above $500
- No guarantee for research and other applications
When do Intel and TSMC expect to use High-NA EUV?
TSMC’s stated production plan
ASML and TSMC said in 2026 that TSMC intends to begin high-volume manufacturing for advanced nodes using High-NA EUV in 2030. That is a company plan, not confirmation that production has already started or that every advanced node will use the technology.
The 12-inch mask initiative
The same 2026 announcement set two related targets: a 12-inch photomask pilot line in 2031 and readiness of 12-inch High-NA systems for advanced-node production in 2033. These milestones describe the mask and system ecosystem’s planned development; they are separate from TSMC’s stated 2030 intention to begin High-NA high-volume manufacturing.
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ASML CEO Christophe Fouquet described the expected progression as: “We expect the adoption of High NA EUV to increase progressively along the device scaling roadmap, first using current 6-inch masks and then further supported by 12-inch masks, which enable greater scanner productivity and allow the industry to meet the demand for smaller, faster and more energy-efficient chips.” The statement points to staged adoption, rather than an overnight switch to a single new format.
Intel’s readiness work
Intel Foundry’s 2026 account describes work with ASML on standards, infrastructure, materials and suppliers needed for High-NA scaling. That indicates ecosystem preparation; it does not establish a specific Intel production start date in the cited statement.
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Does a smaller node mean more transistors?
Not by itself. A process-node label is not a standardized, direct measurement of transistor density, and a smaller-sounding label does not establish how many transistors a particular chip contains. Density depends on the chip’s architecture and layout as well as the manufacturing process.
High-NA can help print finer patterns, but commercially useful scaling also requires design-technology co-optimization: chip designers and process engineers need to adapt designs and manufacturing together. The practical outcome is judged in terms of factors such as density, performance, power, yield and cost—not the node name or scanner resolution alone.
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What could keep the 10-year forecast from coming true?
High-NA supports the case that scaling can continue, but the forecast depends on whether manufacturers can turn the platform into reliable production. The main pressure points are:
- Throughput and process control: tools need to expose wafers at useful production rates while meeting process requirements such as overlay.
- Masks and materials: suitable masks, resists and pellicles must work reliably in manufacturable processes.
- Capital cost: fabs and their customers need to justify the investment with enough production value.
- Yield learning: manufacturers need acceptable yields as they introduce new patterning and process flows.
- Supplier readiness: standards, infrastructure and the wider supplier base must develop alongside the tools.
ASML’s investor disclosure characterizes long-range expectations as forward-looking and subject to risks and uncertainties. The 2030, 2031 and 2033 dates are therefore best read as planned milestones, not guaranteed outcomes.
So, is Moore’s Law dead or merely slowing?
The evidence supports neither a claim that Moore’s Law is dead nor a promise that transistor density will keep doubling on its historical cadence. imec’s roughly 2020 forecast was that it could continue for another 8 to 10 years; the High-NA plans announced by ASML, TSMC and Intel in 2026 provide a technical and ecosystem path consistent with continued scaling. They do not settle whether that scaling will arrive on time, at acceptable cost, or with the same economic gains as before.
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