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RISC-V is an open instruction-set architecture (ISA), not a ready-made processor or system-on-chip. Its public, freely available specifications let different teams build compatible processors, but a working SoC still needs a CPU implementation, memory and I/O, software, verification, and silicon engineering. The distinction is central to understanding what RISC-V makes easier—and what it does not.
What is RISC-V?
An instruction-set architecture defines the instructions a processor can execute and the software-visible rules for using them. RISC-V specifies that interface. It is maintained through a member-led process at RISC-V International, whose specifications are collaboratively developed, ratified, maintained, and freely available. The organization’s FAQ describes the ISA as free and open under a permissive license for use in implementations of all kinds.
The ISA is not the processor’s internal design. Two RISC-V CPUs can implement the same software-visible instructions using different microarchitectures, manufacturing technologies, performance targets, or power budgets. RISC-V International’s ISA introduction identifies implementation independence as a design goal, alongside a small base ISA and optional standard extensions.
Is RISC-V open source?
RISC-V itself is best described as an open standard for an ISA. The openness applies to the specification; it does not mean every RISC-V processor design, tool, or chip is open source. A company can build a proprietary core that implements the public ISA, while a separate project may publish its processor RTL under an open-source license.
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- Flexible MCU Board: Incorporate the ESP32-C3 32-bit RISC-V chip, operating up to 160 MHz, mounted multiple development ports,
- Developer Friendly: Compatible with Arduino IDE, MicroPython, CircuitPython, PlatformIO, ESP IDF, Zephyr, Matter, ESPNow, Meshtastic, WLED, ESPHome, Home Assistant, Ubidots
- Outstanding RF performance: Complete Wi-Fi functions and Bluetooth Low Energy, while supporting communication over 100m with anFL antenna
- Elaborate Power Design: 4 working modes as low as 44 μA in deep sleep mode, while supporting lithium battery charge management
- Thumb-sized Design: 21 x 17.5mm, Seeed Studio XIAO series classic form factor
Nor does access to the ISA automatically provide a verified CPU core, a complete SoC design, a software stack, or a manufactured chip. Those are separate products and engineering efforts. Commercial core-IP vendors remain relevant: RISC-V International’s 2025 annual report identifies functional verification as a barrier and notes that companies began licensing proven, pre-verified RISC-V cores.
How the ISA fits into an SoC
A system-on-chip (SoC) combines one or more processor cores with components such as memory, interconnect, peripherals, and sometimes accelerators. RISC-V gives the processor portion a defined instruction interface; it does not specify every component or integration choice needed to make a product.
A RISC-V implementation starts with a base integer ISA and may add standard extensions. RV32 and RV64 are the 32-bit and 64-bit address-space families. Extensions can add functions such as floating-point, vector, or compressed instructions. Designers choose a supported combination to match the intended product and software; optional extensions are not automatically present in every RISC-V chip.
Rank #2
- CH32V003 Development Minimum System Board for Nano RISC-V CH32V003F4U6 Chip TYPE-C USB 22Pin
- on-board 24MHz Crystal oscillator
- Power by TYPE-C USB
| Family | What the name indicates | Example product context from the ISA model |
|---|---|---|
| RV32 | 32-bit address-space family | A small embedded profile may be appropriate for a microcontroller, depending on the product’s needs. |
| RV64 | 64-bit address-space family | An application-processor or server design may use a richer profile, with platform requirements beyond the ISA itself. |
These are broad families, not complete chip specifications or performance rankings. A product’s actual capabilities depend on its selected extensions, core design, memory system, peripherals, and software.
For an SoC team, the base-and-extension model creates a composition boundary: software can target a defined ISA configuration while the implementation is selected for the product’s workload. The ISA documentation also discusses small SoCs organized as multiprocessor or multicomputer hierarchies, which can support modular development and isolation.
What does RVA23 mean?
RVA23 is an application-processor baseline adopted in the ecosystem milestones highlighted by RISC-V International’s 2025 annual report. A baseline or profile helps define a shared target for implementations and software; it is more specific than saying only that a processor is “RISC-V.” The report’s headline does not, by itself, establish the full extension list or compatibility requirements for a particular product. Check the applicable ratified profile specification and the vendor’s implementation details before treating two RVA23-labelled products as interchangeable.
Rank #3
- The ESP32-C3 SUPERMINI is positioned as a high-performance, low-power, cost-effective IoT mini development board, suitable for low-power IoT applications and wireless wearable applications
- It is equipped with a rich set of interfaces, including 11 digital I/Os that can be used as PWM pins and 4 analog I/Os that can be used as ADC pins.
- It supports four serial interfaces, including UART, I2C, and SPI.
- The ESP32-C3 features a 32-bit RISC-V CPU, including an FPU (Floating Point Unit) capable of 32-bit single-precision
- Package: 2PCS ESP32-C3 MINI Development Board ESP32 SuperMini ESP32 C3 WiFi Module
The same report highlights ratifications during 2025 in server, boot, debug, platform-management, vector-intrinsic, and memory-management specifications. It also notes 15 years of RISC-V, 17 new members, NVIDIA CUDA announced for RISC-V, and preliminary-submitter status at ISO/IEC JTC 1. These are signs of a growing standards and platform ecosystem, not a guarantee that every tool, extension, or vendor implementation is compatible.
What still has to be built or selected?
Building a RISC-V SoC means choosing or developing a processor and completing the surrounding design. The ISA being free removes neither integration work nor the need to establish that the resulting product behaves correctly and meets its requirements.
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- Processor core: select a core IP implementation or develop one, then confirm its ISA base and supported extensions.
- SoC integration: design or select memory, interconnect, interrupt handling, I/O, security features, and any accelerators needed by the product.
- Software: check compiler support, firmware, boot requirements, and the relevant operating system or RTOS. Confirm that the chosen software target matches the core’s ISA and profile.
- Verification and assurance: plan functional verification, conformance checks, security review, and any safety evidence the product requires.
- Implementation and validation: complete physical design, account for foundry and package constraints, and validate the manufactured silicon.
- Lifecycle: assess support, maintenance, specification stability, and the vendor’s roadmap for the product’s expected lifetime.
Custom instructions may help a workload, but they also create a compatibility decision: software and tools must account for them, and another implementation will not necessarily support them. Prefer ratified standards and clearly stated profiles when portability matters; treat draft specifications and vendor-specific additions as dependencies to verify.
Rank #4
- ESP32-C6 WiFi 6 microcontroller development board adopts ESP32-C6-WROOM-1-N8 module, which is equipped with RISC-V 32-bit single-core processor, up to 160MHz main frequency, built-in 8MB Flash
- Integrates WiFi 6, Bluetooth 5 and and IEEE 802.15.4 (Zigbee 3.0 and Thread) wireless communication, with superior RF performance
- Integrates rich peripherals including SPI, UART, I2C, I2S, LED PWM, SDIO and other interfaces, compatible with the pinout of ESP32-C6-DevKitC-1-N8 development board, more convenient to use and expand a variety of peripheral modules
- Onboard CH343 and CH334 USB HUB chips, supports USB and UART development at the same time via a USB-C port
- Comes with online examples and tutorials for ESP-IDF development environment
How to evaluate a RISC-V SoC approach
“RISC-V” alone does not tell you whether a chip is suitable. Compare implementations against the workload and the team’s ability to integrate and maintain them:
- ISA target: identify RV32 or RV64, the required standard extensions, profile compatibility, and any custom-instruction strategy.
- Performance and power: examine the core design, clock target, memory hierarchy, accelerator coupling, and energy envelope. The ISA name alone supplies no performance result.
- Core provenance and verification: distinguish open RTL from commercial core IP, and ask what verification collateral, safety or security evidence, and support lifecycle are included.
- Platform and software: check compiler support, firmware and boot arrangements, Linux or RTOS readiness where relevant, debug support, and whether a usable board exists.
- Integration constraints: account for memory, interconnect, interrupts, I/O, security, foundry, and packaging requirements.
- Governance and compatibility: distinguish ratified specifications from drafts, verify profile stability and conformance, and review the supplier’s roadmap.
For a team building a product, the key comparison is not just the cost of the ISA. It is the total work and risk across core selection, verification, software, integration, and long-term support. An open ISA offers implementation choice; it does not make those choices disappear.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Can you build your own RISC-V chip?
Yes, but “build” can mean several different things. A developer can experiment with RISC-V on an existing board, integrate an available core into an SoC project, or develop a processor and take a design through manufacturing. Each step adds substantially more engineering responsibility. The public ISA specification is a starting point, not a chip-design kit.
Best Value
- Ample PSRAM Storage – The development board offers 8MB PSRAM, providing substantial extra memory for handling more complex tasks, large data buffers, and advanced processing.
- Enhanced Multi-Tasking Capability – With the additional 8MB PSRAM, the ESP32-C5-WIFI6-KIT can efficiently manage multiple protocol stacks simultaneously, ensuring smooth operation in multi-tasking IoT environments.
- Support for Medium-Load Applications – The 8MB PSRAM allows the ESP32-C5 to handle medium-load applications more effectively, making it ideal for scenarios requiring real-time data processing or continuous communication.
- Seamless Performance – The increased memory improves the overall performance and responsiveness of the device, particularly when running applications with larger memory footprints or more demanding computations.
- Future-Proof for Complex Projects – With 8MB of PSRAM, developers are better equipped to build scalable, high-performance solutions that support both current and future IoT use cases, offering flexibility for future-proofing designs.
For a production SoC, decide early whether the team will use open RTL, license a core with verification collateral, or develop its own implementation. Then establish the exact ISA and profile target, software support, verification plan, integration interfaces, and manufacturing path. The 2025 annual report’s discussion of demand for proven, pre-verified cores underscores why licensing remains an option even in an open-ISA ecosystem.
Can RISC-V replace Arm in an SoC?
There is no universal winner. RISC-V’s public ISA gives implementers flexibility to choose or develop cores and extensions. Whether that is an advantage in a particular product depends on its workload, software requirements, verification capacity, integration constraints, and support needs. Compare concrete processor and platform implementations rather than treating either ISA label as a performance, cost, or compatibility guarantee.
What can a RISC-V development board demonstrate?
Raspberry Pi Pico 2 is a practical entry point for firmware experimentation. Its RP2350 microcontroller offers a choice between dual Arm Cortex-M33 cores and dual Hazard3 RISC-V cores. Raspberry Pi specifies operation up to 150 MHz, 520 KB on-chip SRAM, 4 MB flash, USB, SPI, I2C, UART, PWM, and ADC. The official product information lists an open-source C/C++ SDK and MicroPython support.
The Pico 2 is a microcontroller development board, not a Linux-capable application SoC. It can demonstrate RISC-V instruction execution, firmware, peripherals, debugging, and switching between processor architectures on the board. It does not by itself demonstrate the memory subsystem or software platform of a server or desktop SoC. Raspberry Pi lists availability from $5; price and stock can change, so check the current official product information for your region.
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