Handling a high-dI/dt processor load step means designing the entire power-distribution path—not just choosing a regulator. In Robert Kollman’s 17 February 2012 EE Times example, a 1 V rail facing a 100 A/µs load transient and a 3% voltage-excursion limit allows only about 0.3 nH of source inductance. Board traces, vias, package connections, capacitor mounting, and capacitor ESL can each consume a significant part of that budget.
Why is a high-dI/dt transient a power-distribution problem?
When a processor changes operating mode, its current demand can rise very quickly. The regulator may not supply that current instantly, so nearby bypass capacitors must help deliver it. But the current must travel through a complete path: from the capacitors and supply to the load, and back through the return path. Inductance anywhere in that loop resists a rapid current change and contributes to voltage disturbance.
As Kollman puts it, “The key to attacking this problem is to realize that this is not just a power supply problem but a power distribution system problem as well, and the two become intertwined in the solution.” The practical implication is that regulator behavior, PCB layout, package parasitics, and capacitor choice belong in one design, rather than being optimized separately.
How small can the inductance budget be?
For the article’s illustrative case, a 3% excursion on a 1 V rail is 30 mV. With a 100 A/µs current change, the relationship between inductance, current slew, and induced voltage gives an allowable source inductance of about 0.3 nH. This is an example calculation, not a universal limit: the allowable value changes with the rail voltage, permitted excursion, and load-step slew rate.
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| Path element or example | Inductance stated in Kollman’s 2012 article | Why it matters |
|---|---|---|
| 0.1-inch-wide trace on a four-layer board | About 0.7 nH per inch | A short-looking trace can use a substantial fraction of a sub-nH budget. |
| Typical IC-package wire bond | About 1 nH | The package connection alone can exceed the illustrative budget. |
| PCB via | About 0.2 nH | Vias add to the path; their contribution cannot be ignored in a very tight budget. |
| Single 22 µF, X5R, 16 V, 1210 ceramic capacitor | About 1.7 nH series inductance, calculated from resonance near 800 kHz | The capacitor’s effective high-frequency behavior includes its ESL and connection path. |
| Two of the described capacitors in parallel | About 1.0 nH effective inductance | The reduction is meaningful but smaller than the ideal 50% reduction. |
These are the article’s illustrative calculations and measurements, not a standardized benchmark or guaranteed values for every board, package, or capacitor. In particular, mounting can raise a measured capacitor path from about 1 nH to about 1.7 nH. The installed current path—not just a component data-sheet figure—sets the result.
Why doesn’t paralleling capacitors halve the inductance?
For two identical, independent capacitors with ideal connections, paralleling would halve their effective inductance. In a real layout, the capacitors share some interconnect and may couple magnetically; those interconnect and mutual-inductance effects prevent the ideal reduction. In Kollman’s example, two parts reduce the effective inductance from about 1.7 nH to about 1.0 nH, roughly 40%, rather than 50%.
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Adding parts is useful only when their placement and wiring create a lower-inductance path for the changing current. If the branches to the capacitors are long or narrow, or the common path remains inductive, the extra capacitance may not deliver the hoped-for transient improvement.
How close should bypass capacitors be to the load?
Place low-ESL surface-mount bypass capacitors as close to the load as the layout allows, and make the connection between capacitor, load pins, and return short and broad. Minimize the loop area as well as the length of each connection. A nearby capacitor with a long route, narrow trace, or poorly placed via can still have a high-inductance path.
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Consider every segment in the fast-current loop, including PCB traces and vias, package connections, capacitor terminations, and the return path. The regulator remains part of the power-distribution system, but local bypassing is needed because the regulator and its interconnect cannot necessarily deliver a fast load step through an inductive path without voltage disturbance.
Can package size and termination orientation reduce inductance?
Yes, geometry can matter as much as nominal capacitance. Kollman notes that physically larger ceramic capacitors generally have larger inductance. Smaller packages can shorten the current path, while alternate termination layouts can make that path both shorter and broader.
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In the article’s 0805/0508 comparison, the 0508 orientation places the terminations on the longer side, shortening and broadening the current path. Kollman reports a four-to-one inductance reduction relative to the alternative orientation in that example. Treat this as a result tied to the stated design and mounting geometry, not a universal package guarantee; board layout and installation affect the actual inductance.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How should you evaluate a design for a fast load step?
- Set the transient requirement. Specify the rail voltage, maximum permitted voltage excursion, load-step magnitude, and current slew rate. These determine how much inductance the path can tolerate.
- Map the complete current loop. Include the regulator interconnect, PCB traces and vias, package path, capacitor mounting, and return path. Look for long or narrow connections and unnecessary loop area.
- Choose bypass parts by installed path, not capacitance alone. Compare capacitor ESL and package or termination geometry, then account for mounting and shared interconnect inductance.
- Check the effect of parallel parts in the actual layout. Determine whether their branches and shared connections reduce effective inductance rather than assuming an ideal reduction.
- Check regulator stability with the connected bypass capacitance. The regulator must remain stable over the capacitance range used in the design.
- Compare system trade-offs. Weigh achievable transient excursion and path inductance against component, PCB, and assembly cost.
Kollman’s central design lesson is that high-dI/dt loads need careful bypassing to preserve dynamic regulation. A capacitor’s nominal value is only one part of the answer; the geometry and inductance of its complete path determine whether it can help during the transient.
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