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Outbyte PC Repair FREERepair Windows errors before they cause bigger problemsFix Now →Outbyte Driver Updater FREEFix the driver behind crashes, sound loss and screen glitchesFind Drivers →On May 17, 1999, TSMC announced that its CL018 0.18-micron CMOS process was available for production and that it had begun shipping 0.18-micron products. The launch paired a six-metal-layer process using fluorinated silicon glass insulation with an ambitious capacity plan: 34,000 eight-inch wafers in 1999 and more than 600,000 in 2000.
What TSMC announced in May 1999
The announcement marked a move into production, not simply a research milestone. TSMC said CL018 was production-available and that shipments of products made with the process had begun. The company also planned to transfer the process into volume manufacturing, linking the technology announcement directly to factory expansion. EDN reported the launch and capacity plan.
How the six-layer process differed from a simple shrink
TSMC described a process with six metal-interconnect layers and fluorinated silicon glass (FSG) as a low-k insulating material. Roger Fisher, then TSMC’s vice president of marketing, contrasted the approach with processes that were principally 0.25-micron shrinks: “Our observation is that many of the previously announced technologies have been shrinks of 0.25-micron processes, where primarily the gate length was reduced.”
Interconnect pitch and reported density
EDN reported a 0.46-micron pitch for the first metal layer, 0.56 microns for each of the next four layers, and 0.90 micron for the sixth layer. The report said the fine pitch supported 100,000 to 120,000 gates per square millimeter. Those density figures are contemporaneous reported specifications, not an independently established measure of every design’s achieved density.
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FSG insulation
FSG was reported to have a dielectric rating of 3.3 to 3.4, versus slightly above 4 for conventional silicon dioxide. A lower dielectric constant reduces capacitance, a useful property for interconnect performance. These values were reported with the 1999 process announcement.
A second-generation process and copper option
TSMC planned a second-generation 0.18-micron process for the third quarter of 1999, with a 0.13-micron drawn gate length, 1.5-volt core operation, and higher device speeds. Separately, it planned a copper option for the top two metal layers in that quarter.
How quickly TSMC planned to scale production
TSMC’s announced target rose from 34,000 eight-inch wafers in 1999 to more than 600,000 in 2000. These were company production plans, not a report of completed output. EDN also reported that TSMC expected six additional customer tape-outs during the quarter and more than 30 in the second half of 1999, an indication of anticipated design activity rather than a count of completed products.
Which fabs were part of the expansion
- Hsinchu, Taiwan: TSMC planned to transfer CL018 into its volume plants there.
- WaferTech, Camas, Washington: TSMC planned to increase 1999 capital spending for the wafer-fabrication joint venture.
- Fab 6, Tainan, Taiwan: The company planned to equip the fab, which was scheduled to begin processing eight-inch wafers by April 2000.
The locations show that the ramp was not assigned to a single new facility: it combined existing Hsinchu volume capacity, investment in the Camas joint venture, and preparation of a new Tainan fab.
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On December 7, 1999, TSMC announced a commercially available two-layer copper process compatible with its baseline 0.18-micron process. TSMC said the copper interconnect delivered 1.6 times lower metal resistance, up to 15% lower RC delay, 30 to 50 times higher electromigration reliability, and five times lower via series resistance than tungsten plug vias. These are TSMC’s published comparisons, not independent measurements. The company said initial production was in its eight-inch Hsinchu fabs, with full production expected to include Fab 6 in Tainan. TSMC’s December 1999 announcement called it the foundry industry’s first commercially available copper process.
The copper process was described as design-rule compatible with the baseline 0.18-micron process. TSMC also presented it as part of a broader offering that included process access, design services, testing, and customer support—not just a new wiring material.
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How to interpret the launch today
The 0.18-micron label identifies a process generation; it should not be mistaken for a claim that every feature, including drawn gate length, measured exactly 0.18 microns. The planned second-generation variant’s 0.13-micron drawn gate length illustrates the distinction. For comparisons with another historical 180-nm process, useful points include metal-layer count and pitch, dielectric and interconnect materials, voltage targets, production readiness, customer design activity, planned wafer capacity, and fab locations.
TSMC’s current technology page characterizes 0.18-micron logic as a mature, reliable, proven solution for a range of applications; it does not establish the historical ramp figures. TSMC’s current logic technology page provides that present-day context, while the production and capacity figures above belong to the 1999 announcement.
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