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Scan for outdated or missing drivers - takes under a minuteDriver Scan →Clear out junk files and repair common Windows errorsFree Scan →To control scan-shift skew, group scan flops by clock domain and use lockup latches at domain boundaries; for ATPG, choose capture-clock sequences that respect which domains can interact. To verify functional clock-domain crossings (CDCs), use structural analysis and protocol checks, then add formal verification with metastability injection where available. These address different problems: scan techniques make test shifting and capture manageable, while CDC verification checks asynchronous crossings during normal operation.
Why multiple clocks create two different problems
A design with multiple clock domains contains synchronous regions whose clock edges may not align. In functional operation, a signal crossing between asynchronous domains can arrive near the receiving clock edge, causing a setup or hold violation and potentially leaving a receiving flop metastable. Its output may settle to 0 or 1 after an unpredictable delay, as Cadence describes in its CDC-Clean RTL Signoff whitepaper.
Scan test introduces a separate concern: shifting data through a chain that crosses clock domains can expose skew between the clocks. A remedy for scan shifting does not prove a functional crossing safe, and a CDC synchronizer does not by itself solve scan-chain shift timing. Plan for both.
How to control skew while shifting scan data
Group flops by clock domain
Organize scan chains so that flops driven by the same clock domain are grouped together rather than interleaved arbitrarily with flops from unrelated domains. This limits the number of cross-domain transitions within a chain and makes the shift-clock relationships easier to manage. An EE Times article on multi-clock scan recommends grouping flops by domain.
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Insert lockup latches at domain boundaries
Place a lockup latch where the scan path crosses between domains. The latch provides a timing boundary that can prevent skew between scan clocks from corrupting shifted data. The EE Times recommendation is specifically about scan shifting; it is not a substitute for synchronizers or other CDC treatment in functional logic.
Check that the scan architecture, clocking scheme, and ATPG setup agree on where those boundaries are. A misplaced or missing latch can leave a shift path exposed to the very clock skew the partitioning was meant to contain.
How ATPG can reduce multi-clock pattern counts
Give internal domains controllable test clocks
For ATPG capture, EDN recommends providing each internal clock domain with a test-mode clock pin. This gives the test flow explicit control over which domains pulse and when, rather than relying on uncontrolled relationships between functional clocks.
Pulse noninteracting domains together
If two domains have no relevant interaction for a capture condition, their clocks may be pulsed simultaneously. Pulse remaining clocks sequentially when necessary to preserve conservative assumptions about paths that can exist in both directions between domains. Multi-clock compression can then exploit the safe simultaneous pulses while retaining sequential treatment for clocks that cannot safely be combined.
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This is a design- and constraint-dependent choice: whether domains are noninteracting must be established for the capture conditions being tested, not inferred solely from their clock names.
Understand the demonstrated result and its limits
EDN reported a 2002 benchmark with 38,000 gates, 2,120 scan cells, and four clock domains. Clocks 3 and 4 were noninteracting; the compressed runs achieved 99.6% test coverage. That is a result for the reported benchmark, not a general coverage guarantee or a current comparative test across tools.
Weigh D-mimic cells against footprint and at-speed needs
EDN also notes that D-mimic cells can simplify ATPG and minimize patterns, but add footprint and may not support at-speed capture for transition or path-delay fault models. If at-speed testing is a requirement, confirm support for the specific fault model and capture method before choosing this approach. Pattern reduction alone is not a sufficient selection criterion.
What CDC verification should cover
RTL simulation and static timing analysis (STA) are not sufficient on their own for intricate CDC behavior, according to a 2024 paper by Aman Kumar, Muhammad Ul Haque Khan, and Bijitendra Mittra. Simulation may not exercise the critical relative clock timing, while STA cannot by itself establish that a crossing protocol safely handles metastability. A sound sign-off combines structural, formal, and dynamic evidence.
1. Define clock and reset domains
Record which clocks are synchronous, which are asynchronous or otherwise lack a guaranteed phase relationship, and how resets are asserted and released. Make the domain boundaries explicit before reviewing individual crossings.
2. Run structural CDC analysis
Check for missing or misplaced synchronizers, unsafe reconvergence, and combinatorial glitches on signals crossing domains. Treat structural findings as design issues to investigate rather than assuming that a clean timing report has cleared them.
3. Specify constraints and crossing protocols
Document the clock relationships and constraints used by the analysis, along with the protocol that makes each crossing safe. The review should establish what the source may change, how the destination recognizes valid data, and what guarantees apply to resets and handshakes.
4. Add SystemVerilog assertions and formal checks
Use assertions to express the crossing protocol, then run formal checks. The 2024 paper proposes metastability injection in a formal flow to expose behaviors that ordinary RTL simulation may miss. This supplements—not replaces—structural analysis and protocol reasoning.
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5. Exercise IP and SoC behavior in simulation
Use simulation and coverage models at both IP and SoC levels to test interactions in realistic integration contexts. A reusable IP block may meet its local assumptions but encounter different clock or reset relationships in the SoC, so the integration-level checks matter.
Synopsys notes that modern SoCs can contain dozens, and sometimes hundreds, of asynchronous clock domains, which is one reason conventional simulation or STA should not be treated as the sole CDC sign-off evidence. Accellera’s 2024 workshop addresses hierarchical CDC/RDC, vendor abstract models, setup and constraints, structural checks, and CDC assertions—useful topics when defining a flow across reusable blocks and tools.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to choose an approach for a design
| Approach | Primary purpose | Trade-off or qualification |
|---|---|---|
| Domain-grouped scan chains with boundary lockup latches | Control scan-shift exposure to skew across domains | EE Times recommends this for scan shifting; it does not establish functional CDC safety. |
| Test-mode clock pins, safe simultaneous pulses, and multi-clock compression | Reduce ATPG pattern count while controlling capture sequencing | Simultaneous pulses depend on domains being noninteracting for the capture condition. EDN’s 99.6% coverage figure is from its specific 2002 benchmark. |
| D-mimic cells | Simplify ATPG and potentially minimize patterns | EDN reports increased footprint and possible lack of support for at-speed transition/path-delay capture. |
| Structural CDC analysis, assertions, formal checks with metastability injection, and simulation | Build functional CDC sign-off evidence | These methods address different failure modes; RTL simulation or STA alone is insufficient for intricate CDC issues, according to the 2024 paper. |
When comparing implementations, assess shift-skew control, capture-clock flexibility, pattern count and runtime, area, at-speed transition/path-delay support, the mix of structural/formal/dynamic coverage, and portability across IP and vendor flows. The sources cited here do not provide a current head-to-head measurement of tool runtime, area, or pattern-count reductions across products, so those values should be established against the design’s own constraints and fault models.
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