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Random freezes, missing sound and display glitches usually trace back to one bad driver. Find and replace yours safely.Free scan · under a minuteYes—IBM Research demonstrated deep-neural-network training with 8-bit floating-point (FP8) arithmetic while maintaining accuracy across the models and datasets it tested. The work progressed from a 14 nm test-chip layout described in 2018 to a four-core 7 nm research chip reported in 2021. IBM published performance figures for that chip, but the sources describe research silicon, not a named retail product available to buy.
What does 8-bit AI training mean?
Neural networks perform large numbers of multiplications and additions. Those operations are often carried out with floating-point values, which represent a range of numbers with finite precision. FP32 uses 32 bits per value; FP8 uses eight. Reducing the number of bits can make arithmetic hardware smaller and more energy-efficient, but it can also introduce enough numerical error to degrade training.
IBM’s result was not simply a claim that any model can be trained by switching all calculations to ordinary 8-bit values. IBM developed a hybrid approach that uses 8-bit multiplications and 16-bit additions in core matrix and convolution operations, along with techniques to address the numerical problems that arise during training. The work was reported in 2018 in IBM Research’s account of 8-bit deep-learning training.
How IBM addressed the precision problem
IBM identified three obstacles to training below 16-bit precision: low-precision operands can reduce accuracy, short accumulators can lose information in long dot products, and low-precision weight updates can interfere with convergence. The approach combines an FP8 format with special handling for the first and last network layers, chunk-based accumulation, and stochastic rounding for updates.
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FP8 with special handling at the network edges
IBM’s format and training method account for layers that can be especially sensitive to reduced precision. Rather than treating every operation as interchangeable, the method applies special handling to the first and last layers while using reduced-precision arithmetic in the core matrix and convolution work.
Chunk-based accumulation
A long dot product may combine many products. Accumulating all of them in a short register can discard small contributions. IBM’s hierarchical chunk-based method divides accumulation into pieces so that intermediate values can be combined with more care, limiting the information lost during long calculations.
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Stochastic rounding for updates
Training repeatedly updates model weights. Rounding every small update in the same deterministic direction can impede learning when the update is too small to be represented directly. Stochastic rounding varies the rounding outcome probabilistically, helping preserve the effect of small updates over time.
IBM reported accuracy on par with FP32 across the models and datasets it tested. That finding applies to those experiments; it is not a guarantee for every model, dataset, training recipe, or deployment.
What the hardware demonstrated
2018: a 14 nm test-chip layout
IBM’s 2018 account described a 14 nm technology test-chip layout. Its chunk-accumulation engines worked alongside reduced-precision dataflow engines, which IBM said could be done without significant hardware overhead. The article also cited a potential 2–4× throughput improvement and more than 2–4× training-energy improvement. These are IBM Research’s stated potential gains, not independently validated comparisons against a specified commercial accelerator.
2021: a four-core 7 nm chip
In a January 17, 2021 IBM Research account, IBM described a four-core chip built using 7 nm EUV technology and called it the first silicon chip to incorporate hybrid FP8 formats for deep-learning training. IBM reported 25.6 TFLOPS of hybrid-FP8 training performance and 102.4 TOPS of INT4 inference performance. In IBM’s measurements, training utilization exceeded 80%, while inference utilization exceeded 60%.
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- ✅Supports Linux and Windows. Supports the temperature range of -40°C to 85°C
These figures describe different operations and number formats: hybrid-FP8 training and INT4 inference. They should not be read as a like-for-like comparison with a commercial product’s benchmark unless workload, precision, and measurement conditions also match. IBM said the chip’s cores communicate through multi-core protocols, but the account does not establish that the chip became a retail accelerator or that it is shipping in products.
How FP8 fits alongside other AI precisions
| Format or approach | What the IBM material establishes | Use described |
|---|---|---|
| FP32 | Reference precision used when comparing training accuracy | Accuracy comparison in IBM’s tested models and datasets |
| FP8 | IBM’s hybrid approach uses 8-bit multiplications with 16-bit additions in core matrix and convolution operations | Deep-learning training |
| INT4 | IBM reported 102.4 TOPS on its 7 nm chip | Inference |
The table reflects the cited IBM work; it does not rank all implementations of these formats or establish performance across vendors.
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Is IBM’s FP8 chip available to buy?
The cited IBM accounts describe research hardware and published silicon results, not a named retail chip, accelerator card, or development board. They provide no purchase route or commercial availability details. IBM’s stated target workloads—including vision, speech services, natural-language processing, fraud detection, autonomous vehicles, security cameras, mobile devices, and federated learning—describe intended application areas, not proof that a commercial product is shipping.
How to experiment with related IBM software
Researchers interested in hardware constraints can explore IBM’s software projects, which are separate from the FP8 chip. AIHWKit provides an open-source simulator for analog crossbar arrays and supports hardware-aware training and inference. AIHWKit-Lightning focuses on scalable hardware-aware training for larger models. These projects concern analog hardware workflows; they do not give users access to IBM’s FP8 research silicon.
FP8 is not the same as IBM’s analog AI work
IBM’s FP8 demonstration uses digital arithmetic. Its separate analog AI program uses phase-change-memory arrays to compute matrix operations in memory, aiming to reduce data movement across the von Neumann bottleneck. Analog deployments bring their own constraints, including converter behavior, noise, and device failures, which hardware-aware training must take into account.
IBM also reported an analog inference chip with 64 tiles, 8-bit input-output matrix multiplications at 400 GOPS/mm², and 92.81% CIFAR-10 accuracy. Those figures concern analog inference, not the digital FP8 training chip, and should not be combined with its training results.
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