Altos Design Automation introduced Liberate in 2006 to automate the creation of standard-cell and I/O libraries from transistor-level SPICE data. Its central pitch was that inspecting each cell’s transistor connectivity could cut redundant simulations and speed characterization—an increasingly important task as semiconductor libraries grew more complex.
What was Liberate?
Liberate was an electronic-design-automation (EDA) tool for converting SPICE netlists and subcircuits into characterized library data used by static-timing analysis flows. In practical terms, it helped semiconductor design teams describe how standard cells and I/Os behave under specified operating conditions so timing tools could use those models.
EE Times reported the product’s introduction from Santa Cruz, California, on July 3, 2006. It was Altos Design Automation’s first product, aimed at semiconductor design organizations, IP vendors and library teams—not a consumer software product.
Why did library characterization become a bottleneck?
At 90-nanometer process technology and below, library teams had to manage more views, threshold-voltage options, dynamic-voltage-scaling conditions, and voltage and temperature corners. Each additional condition could require more simulation and data, making library creation substantially more demanding.
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The 2006 EE Times report said process variations could make library construction take 20 to 100 times longer. That figure describes the problem as reported at the time; it is not an independently verified benchmark of Liberate’s performance or a measure for present-day design flows.
How did Liberate aim to reduce simulation work?
Altos’ differentiator was an “inside view” of a cell. Rather than treating every input-vector sequence as an unrelated case, Liberate could inspect transistor connectivity and cell function, identify sequences that were electrically equivalent, and omit redundant simulations. Fewer simulations were intended to reduce characterization runtime.
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Altos claimed this approach delivered a ten-fold speedup in cell-library characterization. EE Times reported the claim, but the available account does not provide an independent benchmark, test conditions, or a silicon-correlation study to verify it.
What went into the flow, and what did it produce?
Users supplied SPICE netlists and subcircuits. Liberate then generated characterized cell libraries for use with existing static-timing analyzers. It supported the Composite Current Source (CCS) model associated with Synopsys and the Effective Current Source Model (ECSM) associated with Cadence Design Systems and Magma Design Automation, according to the 2006 report.
The product included an integrated SPICE simulator, while also allowing a team to call a third-party simulator. That gave users a choice between using the simulator bundled with Liberate and retaining an external simulator in their characterization flow.
What did Altos propose for statistical timing?
Altos described Variety as a planned superset of Liberate. The proposed product would add process-parameter variation effects and generate statistical libraries accounting for random and systematic variation. The EE Times article said Variety was slated for the third quarter of 2006; that is a reported schedule, not confirmation that it shipped on that date.
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The roadmap addressed a specific modeling challenge: statistical timing depends on library data that captures variation, while the growing number of operating conditions already made characterization more burdensome. The article presents Altos’ intended direction, but does not establish Variety’s later release, capabilities, or commercial status.
How was Liberate sold?
EE Times reported a starting price of $95,000 for a one-year license in 2006. The article does not specify maintenance terms or other licensing conditions, and this historical figure should not be read as a current price.
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Who founded Altos, and what happened to the company?
Ken Tseng, Altos’ chief technology officer, and Kevin Chou, its vice president of research and development, launched the company in January 2005. Both had worked at CadMOS Design Technology before Cadence acquired CadMOS in 2001; at Cadence, they were key developers of the CeltIC crosstalk-analysis tool. Jim McCanny, another CadMOS alumnus, joined Altos as CEO in July 2005.
Cadence’s company history records that it acquired Altos Design Automation in May 2011. That establishes Altos’ corporate outcome, but does not by itself identify Liberate’s current product name, support status, or price. Those details are not established by the available historical account.
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