At the International Test Conference in 2000, Synopsys and Mentor Graphics announced upgrades aimed at different bottlenecks in chip testing. Synopsys linked scan-chain ordering to physical placement and added sequential test-pattern generation; Mentor rewrote its boundary-scan tool and added pattern compression to FastScan. The reported gains—less wiring congestion, higher test coverage, and fewer test patterns—were vendor claims reported at the time, not current product specifications.
What the companies announced
EE Times reported on October 2, 2000, that Synopsys announced upgrades to DFT Compiler and TetraMax ATPG, while Mentor Graphics announced BSDArchitect New Edition and FastScan 2001. DFT, or design for test, comprises design and software techniques that make it easier to test a chip during manufacturing. Scan chains, boundary scan, and automatic test-pattern generation (ATPG) are distinct parts of that work.
| Tool and period release | Primary role | What changed |
|---|---|---|
| DFT Compiler 2000.11 | Scan-test synthesis and implementation | Physical Compiler placement-aware scan ordering, RTL testability analysis, automatic scan-rule repair, and synthesis under timing, area, and power constraints. |
| TetraMax ATPG 2000.11 | Automatic test-pattern generation | Added sequential ATPG to existing combinatorial and limited-sequential capabilities. |
| BSDArchitect New Edition | Boundary-scan design | Replaced an OEM-resold implementation with Mentor’s rewritten technology; added I/O-pad synthesis, DC parametric test generation, and memory-BIST interface synthesis. |
| FastScan 2001 | ATPG | Added pattern compression, synchronous macro test for small embedded memories, fault sampling, and a Unix K-shell command-line environment. |
What Synopsys changed
DFT Compiler used physical placement to improve scan implementation
Scan chains connect a chip’s scan-capable registers so test data can be shifted in and observed. The 2000.11 release could use Physical Compiler placement information to reorder those chains. The integration was exposed as a Physical Compiler command, with the aim of reducing scan wiring congestion and helping timing closure.
Synopsys also added RTL testability analysis, automatic repair of scan-design-rule violations, and scan-chain synthesis constrained by timing, area, and power. Synopsys product marketing manager Mouli Chandramouli told EE Times the company had seen “easily 10 to 15 percent less wiring congestion” in its benchmarks. He also said the integration optimized scan-chain ordering and fixed setup- and hold-time violations on scan chains. These are company-reported results, not a guarantee for every design.
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TetraMax added sequential ATPG
ATPG generates patterns intended to expose manufacturing faults. TetraMax ATPG 2000.11 added sequential pattern generation to its existing combinatorial and limited-sequential methods. Synopsys positioned the feature for designs with embedded memories, large register arrays, and legacy blocks with limited scan access.
The contemporaneous report said many designs saw a 5 to 10 percent improvement in test coverage. It also repeated an industry figure that raising coverage from 93% to 97% can reduce defective parts shipped by 50%. That comparison is an attributed industry estimate in the report, not an independently verified result or a universal conversion between coverage and shipped defects.
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What Mentor changed
BSDArchitect New Edition was rebuilt
Boundary scan provides a way to test interconnections through circuitry at a chip’s I/O boundary. Mentor replaced its OEM-resold BSDArchitect implementation with its own rewritten technology. Product marketing manager Ian Burgess described the release as a “rewrite from top to bottom.”
New functions included automatic synthesis of I/O pads, generation of DC parametric tests, and direct control of memory-BIST architectures by synthesizing interfaces to memory structures. The announcement emphasized automation around boundary-scan and memory-test setup, rather than a reported percentage improvement in coverage or cost.
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FastScan already supported combinatorial and sequential ATPG. Its 2001 upgrade added pattern compression aimed at designs with multiple clocks, synchronous macro test for small embedded memories, fault sampling, and a Unix K-shell command-line interface.
Mentor said the new algorithms could reduce pattern counts by 20 to 60 percent while maintaining the same coverage level. The practical value was smaller test-vector sets for manufacturing. Mentor general manager Fred Cohen said test-vector data “typically takes around 500 bytes per gate,” illustrating why multi-million-gate designs could produce gigabyte-scale test data. Both figures were Mentor statements reported by EE Times, not independent measurements applicable to every chip.
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How the upgrades addressed manufacturing cost
The announcements targeted different contributors to test expense rather than one shared cost metric:
- Wiring and timing: placement-aware scan ordering was intended to reduce congestion and ease timing closure, potentially avoiding implementation problems in scan paths.
- Fault detection: sequential ATPG addressed designs that were difficult to cover with combinatorial patterns alone. Higher coverage can matter to outgoing quality, although the article’s 93%-to-97% defective-shipment comparison should be treated as a cited industry claim.
- Test-data volume: FastScan’s reported pattern reduction could reduce the data that equipment must store, transfer, or apply, while holding coverage constant according to Mentor.
- Setup effort: automated scan-rule repair, RTL analysis, pad synthesis, and memory-BIST interface generation aimed to reduce manual DFT work.
These are related but not interchangeable outcomes. Pattern count, test coverage, wire congestion, and defect rates measure different things; the 2000 announcements do not establish a single quantified reduction in total manufacturing cost.
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Period prices and availability
The prices below are starting prices reported in 2000, not current quotes or evidence of present-day availability. Release timing and availability also refer to the period of the EE Times article.
| Product | Timing reported in 2000 | Starting price reported in 2000 |
|---|---|---|
| DFT Compiler 2000.11 | Planned to ship in December 2000 | $15,000 |
| TetraMax ATPG 2000.11 | Planned to ship in December 2000 | $33,500 |
| BSDArchitect New Edition | Available at the time of the article | $50,000 |
| FastScan 2001 | Available at the time of the article | $92,400 |
How the tools fit into later DFT developments
The 2000 products are historical releases, not a guide to current product names or purchasing options. Synopsys’ current TestMAX DFT datasheet describes a broader integrated flow spanning boundary scan, scan chains, core wrapping, test points, compression, RTL validation, IEEE 1687 and IEEE 1500 access networks, and integration with Design Compiler and Fusion Compiler.
In 2018, Synopsys described Test Fusion as combining SpyGlass DFT testability analysis, DFTMAX test synthesis, Synopsys synthesis, and TetraMAX II ATPG. The company said new test-point functionality reduced manufacturing test costs by an average of 40%; this was a vendor-reported figure in its 2018 announcement, not an independently established result.
In 2026, Synopsys and Samsung Foundry said TestMAX with AI-assisted ATPG helped reduce test patterns and test cycles by up to 20% while preserving fault coverage on cited SoC and multi-die designs. Their announcement frames that figure for those designs; it should not be generalized to every manufacturing flow.
For Mentor’s later ecosystem, TSMC’s Reference Flow 8.0 announcement in 2007 documents flows using Mentor DFT tools based on Calibre and TestKompress. It shows continued integration into a foundry reference methodology, but does not establish the current availability or naming of BSDArchitect or FastScan.
Quick Recap
Sources
- EE Times, “Synopsys, Mentor spiff up design-for-test tools,” October 2, 2000.
- Synopsys TestMAX DFT product information.
- Synopsys, Test Fusion announcement, 2018.
- Synopsys and Samsung Foundry announcement, 2026.
- TSMC Reference Flow 8.0 announcement, 2007.
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
