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A 2021 study demonstrated a 2 × 2 array of one-transistor SRAM cells built with single-gated feedback field-effect transistors (FBFETs). The authors reported promising cell-level retention, read, endurance and standby-power results. But the small array is a research demonstration—not proof of a drop-in, commercially deployed replacement for conventional CMOS SRAM. Fewer transistors per cell could help memory density, but transistor count alone does not determine how much usable memory fits on a chip.
How can SRAM store a bit with one transistor?
A conventional six-transistor SRAM cell uses multiple transistors to hold and access a bit. The 2021 demonstration took a different approach: it used a single-gated feedback field-effect transistor, or FBFET, as the storage device. The feedback behavior is central to the proposed one-transistor cell; it is not simply a conventional six-transistor cell with five devices removed.
The study fabricated a 2 × 2 array and reported reading a selected cell without disturbing the half-selected cells in that array. That is evidence that the cells could operate together at a small array scale. It does not establish how a much larger memory would behave or how its access and control circuits would affect total chip area.
What did the 2021 FBFET study report?
The authors reported the following results for their one-transistor FBFET SRAM. They are results for the studied devices, not guarantees for every one-transistor SRAM architecture.
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| Measure | Reported result | What it describes |
|---|---|---|
| Retention | More than 900 seconds | Reported individual-cell retention. |
| Read behavior | Nondestructive reading for 10,000 seconds | Reported individual-cell read result; the authors also reported nondestructive selected-cell reading in the 2 × 2 array without disturbing half-selected cells. |
| Endurance | 108 cycles | Reported endurance for the studied device. |
| Estimated standby power | 0.7 pW holding “0”; 6 nW holding “1” | Authors’ state-dependent standby-power estimates. |
These figures are encouraging but should be read with the scale and evidence type in mind: the physical array contained four cells, and the numeric results are the study authors’ reports. They do not by themselves establish production-scale reliability, a manufacturing process, or independent replication.
Does one transistor mean six times the memory density?
No. A one-transistor cell has a lower transistor count than a six-transistor cell, but that does not translate directly into a sixfold reduction in memory area. The cell’s physical footprint depends on device layout and process integration, while a working memory also needs circuitry to select cells, read and write data, and connect the array to the rest of the chip. The 2 × 2 result does not establish the area of a production memory macro or its peripheral circuitry.
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A historical IBM result illustrates why raw area figures need context. Subbanna and colleagues reported a 6.9 μm² embedded SRAM cell using 0.25 μm design-rule salicide CMOS; functionality was also demonstrated at 0.35 μm design rules. That 1996 result is useful background on embedded CMOS SRAM, but its cell area is not a fair direct density comparison with the later FBFET array: the devices, processes and demonstrations differ.
How does it compare with established six-transistor SRAM?
Conventional six-transistor SRAM remains an active design space, with trade-offs among read stability, leakage and writing. For example, He and colleagues reported an asymmetric 6T cell fabricated in 0.13 μm partially depleted SOI CMOS. Against a symmetric 6T baseline, it improved measured read stability by 43% and reduced cell leakage by 24%, while requiring additional write current.
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That result is not a head-to-head comparison with the FBFET cells: it concerns a different architecture, process and study. It shows why device count alone is not enough to judge a memory design. A practical comparison also needs compatible measurements of array behavior, read disturb, write current and margin, power, process integration and scale.
What about other one-transistor SRAM proposals?
“One-transistor SRAM” does not identify one universal device or maturity level. Dutta and colleagues’ 2021 paper on one-transistor bipolar SRAM presented a macro-compact model built from MOSFETs, a bipolar junction transistor and passive components, calibrated with TCAD results at the 28 nm technology node. This was a modeling study, not evidence of a fabricated 28 nm product or the same FBFET array architecture.
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Keeping the proposals distinct matters: the FBFET paper reports a fabricated small array, while the bipolar SRAM paper reports a compact model. Neither should be treated as proof that a commercially available one-transistor SRAM has replaced conventional CMOS SRAM.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What would establish a practical density advantage?
The FBFET result makes a case for further investigation, not a settled production advantage. To judge whether this approach could pack more usable memory into CMOS, readers would need evidence beyond the transistor count and four-cell array, including:
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- larger arrays showing reliable selection and read/write behavior across many cells;
- the total area of the memory macro, including access and peripheral circuitry;
- write voltage, current and margin alongside retention and read-disturb behavior;
- power and reliability results under clearly specified operating conditions; and
- evidence of process integration and manufacturing suitability.
Until those questions are answered, the sound conclusion is narrow: a 2021 study demonstrated a four-cell FBFET-based one-transistor SRAM array and reported notable cell-level results, but it did not establish a production-ready or commercially deployed CMOS SRAM replacement.
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