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Repair common Windows errors and clear accumulated junk for a smoother, more stable PC - no reinstall needed.Free scan · no reinstallFully depleted silicon-on-insulator (FD-SOI) is a planar CMOS technology in which the transistor channel is formed in a very thin silicon film above a buried oxide (BOX). The thin body becomes depleted through its thickness during operation, while the BOX electrically isolates the device layer from the silicon substrate. This combination improves electrostatic control and can allow a designer to adjust threshold voltage with a back-bias voltage.
What is fully depleted silicon on insulator?
In a conventional planar MOSFET, the channel is formed in a comparatively thick silicon substrate. In an FD-SOI transistor, the active silicon is a thin layer separated from the handle wafer by an insulating buried oxide. The silicon body is thin enough that depletion extends through the entire body rather than leaving a neutral silicon region beneath the channel; hence fully depleted.
FD-SOI remains a planar technology: transistors are laid out on the wafer surface rather than using the three-dimensional fin of a FinFET. The exact silicon-film and BOX thicknesses are process-specific. A review of a platform developed toward the 28 nm generation describes a silicon film below 10 nm and an approximately 25 nm ultra-thin BOX. Those values characterize that reviewed generation, not every FD-SOI process.
How does an FD-SOI transistor work?
The device stack
- Top silicon film: The transistor source, channel and drain are formed in the thin device layer.
- Gate dielectric and gate: The gate controls carrier concentration in the channel, as in other MOSFETs.
- Buried oxide: The BOX electrically separates the device layer from the underlying substrate.
- Handle wafer: The substrate can serve as an electrical back gate when the process provides a suitable back-bias structure.
Full depletion and electrostatic control
Because the body is thin, the gate has stronger control over the channel potential and short-channel behavior. The undoped or very lightly doped channel used in FD-SOI also avoids relying on heavy body doping to set transistor behavior. Reduced junction area and isolation through the BOX can lower junction leakage and parasitic capacitance, although the result still depends on the complete process and circuit layout.
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Back-biasing through the BOX
An ultra-thin BOX allows the substrate-side electrode to influence the channel. Applying back bias shifts threshold voltage: forward body bias can favor speed, while reverse body bias can reduce leakage. Designers can therefore tune a circuit’s power-performance point dynamically or select different operating conditions. The usable voltage range, reliability limits and circuit benefit are specific to the foundry process and design rules; back bias is not an unlimited substitute for sizing, voltage or frequency optimization.
Potential advantages
- Isolation: The BOX provides dielectric isolation between the transistor layer and substrate, reducing some substrate-coupling paths.
- Lower parasitics: Smaller junctions and reduced junction capacitance can improve switching and energy behavior.
- Thin-body control: Full depletion gives the gate strong control of the channel as dimensions shrink.
- Threshold adjustment: Back bias can move threshold voltage without changing the front-gate stack.
- Planar implementation: Existing planar layout concepts and multi-threshold options can be retained in suitable design kits.
These are mechanisms and possible benefits, not guaranteed specifications. Performance, leakage, variability, manufacturability and power depend on the particular process, libraries, voltages, temperature range and circuit.
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What are FD-SOI devices used for?
Low-power digital logic
FD-SOI is considered for processors, controllers and other CMOS logic where energy efficiency and operation across several performance modes matter. Back-bias control can support a fast mode and a low-leakage mode, but the actual advantage must be demonstrated at the target workload and operating point.
High-performance CMOS
The same electrostatic control and threshold-tuning mechanisms can be used to pursue higher frequency when the process and design library support it. A claim about performance should identify the node, voltage, temperature, library and circuit rather than treating “FD-SOI” as a single performance class.
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RF and mixed-signal circuits
Earlier device research evaluated FD-SOI process technology for digital and RF applications. The BOX can reduce some substrate interaction, while the device layer and body configuration affect capacitance, noise and linearity. RF suitability therefore requires measurements for the intended frequency, layout and bias conditions; historical RF results do not establish behavior in current nodes.
Measured dimensions and why they need qualification
A 2025 peer-reviewed wafer-characterization study examined an FDSOI wafer with a reported 12 nm silicon film and 25 nm BOX. Its measured electrical properties changed with bias, frequency, excitation amplitude, light exposure and oxide thickness. These observations describe that wafer and those measurement conditions. They should not be read as universal dimensions or operating behavior for all FD-SOI products.
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FD-SOI design trade-offs
| Decision axis | Questions to answer |
|---|---|
| Power and performance | What energy, frequency and leakage are achieved at the required voltage, temperature and workload? |
| Back bias | What forward- and reverse-bias range is allowed, and is a bias generator or control loop required? |
| Process and libraries | Are the required standard cells, memories, analog models, RF devices and multi-threshold options available? |
| Variability and manufacturability | How do local variation, wafer variation, body thickness and process tolerances affect yield and margins? |
| RF or mixed signal | Do substrate coupling, noise, capacitance and linearity meet the circuit specification? |
| Ecosystem and cost | Can the foundry, intellectual-property portfolio, packaging flow and production capacity support the product? |
There is no process-independent winner. A meaningful comparison with bulk CMOS or another platform must use equivalent circuits, design rules, operating points and production assumptions. The reviewed literature identifies scaling, manufacturability, variability and power-performance trade-offs as continuing engineering issues.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Historical performance evidence
A 2004 study reported approximately 60% power reduction versus bulk CMOS while maintaining operating speed for the devices and conditions in that study. That is a historical, study-specific result—not a current-node promise or a figure that can be applied to every FD-SOI design.
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How to evaluate an FD-SOI process
- Define the product’s voltage, frequency, temperature, lifetime and workload targets.
- Obtain the foundry’s process design kit and verify device models, design rules, back-bias limits and reliability specifications.
- Compare matched circuits using the same libraries, memory assumptions, package and operating conditions.
- Characterize leakage, delay, noise, variability and RF behavior across process, voltage and temperature corners.
- Assess production capacity, intellectual-property support, yield learning and long-term ecosystem availability before committing to the platform.
Further reading
For a specialist treatment of device physics, electrical characterization and advanced structures, Elsevier’s first edition of Fully Depleted Silicon-On-Insulator is a suitable technical reference. Availability should be checked with the publisher or bookseller.
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