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One free scan finds every outdated or missing driver and matches the right update for your exact hardware.Free scan · exact hardware matchIntel’s captive Mask Operations aimed to give the chipmaker tighter control over photomask quality, cost and delivery as shrinking features made masks harder to produce. In a January 24, 2003 report, EE Times said Intel claimed it could deliver the first three critical mask layers in five days, compared with seven to twelve days at merchant mask shops. Those figures describe Intel’s historical claim and the article’s comparison—not a current benchmark.
What is a photomask?
A photomask is a plate carrying a pattern that lithography uses to project circuit designs onto a silicon wafer. A chip is built through repeated patterning steps, and masks are part of the process that turns a design into physical features. Defects or delays in mask production can therefore affect manufacturing readiness.
Intel’s 2000 announcement described more than 20 photomasks being used to manufacture a product in then-state-of-the-art silicon CMOS. That is a period-specific figure, not a current mask count. Intel’s January 17, 2000 release also documented a photomask-technology collaboration with Dai Nippon Printing.
Why did Intel operate its own mask shop?
EE Times described Intel Mask Operations as a captive operation intended to give Intel control over high-end masks and bring materials suppliers, mask production, chip design and fabs into closer coordination. The strategic point was not simply making masks in-house: tighter coordination could help synchronize a complex component of manufacturing with design and fab needs.
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Intel’s Chiang Yang, then general manager and director of technology for Intel Mask Operations, said: “Intel’s internal mask shop provides us with a competitive advantage.” That statement was Intel’s rationale, not independent proof that the captive model outperformed outside suppliers in every respect.
Why are semiconductor photomasks so expensive?
As circuit features shrank, the report said, lithography wavelengths and optical limits did not shrink at the same pace. Mask makers therefore had to use increasingly sophisticated techniques to make printed patterns match the intended design. EE Times quoted Barry Lieberman, Intel Mask Operations engineering manager: “Mask complexity is increasing faster than device complexity.”
The 2003 article cited these historical estimates and claims:
| Item | Reported figure | Qualification |
|---|---|---|
| 90-nm mask cost | $800,000–$1.3 million | Estimate attributed to Lieberman and reported by EE Times in 2003. |
| Potential 65-nm mask-set cost | $2 million or more | Intel officials’ indication as reported by EE Times in 2003; higher future amounts in the report were expert speculation. |
| First three critical mask layers | Five days for Intel; seven to twelve days for merchant shops | Intel’s cycle-time claim and the article’s merchant-shop comparison, reported in 2003; not independently audited or current. |
These are historical figures tied to the article’s period and technology nodes. They should not be treated as present-day mask prices or delivery times.
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1Scan for outdated or missing drivers - takes under a minute2Clear out junk files and repair common Windows errors3Fix the driver behind crashes, sound loss and screen glitchesWhat is the mask maker’s burden?
The burden described in the report was to create masks that could faithfully produce ever-smaller features while managing defects, measurement and repair. Intel had demonstrated a prototype 65-nm photomask using 193-nm lithography and resolution-enhancement techniques. The report discussed phase-shift masks and optical proximity correction as ways to address the widening gap between feature size and the wavelength and optical limits of the lithography system.
EE Times reported that Intel used electron-beam tools for critical layers and pattern generators for less critical portions, along with inspection, metrology and repair equipment. Some equipment details were attributed to unnamed sources. It also named defect-management modules called Callas, Tebaldi and Primadonna, coordinated by a “Divas Server.” These are details reported about Intel’s operation in 2003; they do not establish Intel’s current equipment or internal systems.
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How do EUV masks differ from conventional masks?
Conventional deep-ultraviolet (DUV) masks transmit light through a patterned mask. EUV light is absorbed by air and most materials, so an EUV mask must reflect the light instead. Intel’s 2001 technical release described an EUV mask built on a low-thermal-expansion substrate with a multilayer silicon/molybdenum reflector. Intel said its announced EUV mask would print a minimum feature size of 50 nm—a historical demonstration figure, not a current capability statement. Intel’s March 8, 2001 release explains the mask structure and announcement.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What does mask stitching mean for High-NA EUV?
In a September 7, 2026 announcement, Intel Foundry and ASML said Intel was using High-NA EUV in production, including select layers for a subset of Core Ultra Series 3 processors (Panther Lake). They also reported more than one million wafers processed with High-NA EUV across early tool certification and testing, R&D, and volume production. That combined total is not a count of commercial production wafers alone.
For mask format, Intel Foundry said designers can use the existing 6-inch mask format either by fitting a design within its field or by using Intel’s stitching capability and process design kit solutions. Stitching allows a design to be handled across joined exposure fields rather than forcing it all to fit within one field. Intel and ASML also described work to develop a larger 6×12-inch mask ecosystem; the announcement does not say that this larger format is already the production standard.
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Intel Foundry described the existing-format approach this way: “Customers can realize the benefits of High NA using the industry’s current mask format, either by floor-planning within the 6-inch mask or by utilizing Intel Foundry’s stitching capabilities and process design kit (PDK) solutions.” The companies’ announcement describes these approaches but does not provide comparative cost or performance measurements. Intel Foundry and ASML’s September 7, 2026 announcement gives their account of production use and mask-format work.
What the 2003 report does—and does not—show
The report captures Intel’s effort to treat masks as a strategic manufacturing capability at a time when complexity and cost were rising. It offers period-specific claims about turnaround, equipment and cost, plus Intel’s argument for closer control of the design-to-fab chain. It does not establish current supplier rankings, present-day mask costs or delivery times, or the current contents of Intel’s mask-shop toolset.
