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You can build a 1:10-scale Cray-1 as a physical model, an FPGA recreation of selected Cray-1 behavior, or both. The strongest documented example combines the two: Chris Fenton described a binary-compatible, cycle-accurate recreation running on a Xilinx Spartan-3E 1600 board, alongside a hand-fabricated 1:10 enclosure. Treat those as separate projects with a shared goal: first choose how much of the original machine you want to reproduce, then plan the electronics and case accordingly.
Choose what “build a Cray-1” means for your project
A detailed case does not make a computer functional, and an FPGA that runs Cray-like code does not automatically reproduce the original machine in full. Decide which outcome you want before buying parts or drawing the enclosure.
Display model
Build the C-shaped cabinet, panels, badge, and settee without functional computing hardware. This is the most fabrication-focused route; you can use a simple light or display effect if desired, but that is separate from recreating Cray-1 behavior.
FPGA recreation of selected behavior
Implement and test a defined subset of the architecture on an FPGA. Set an explicit boundary—for example, which instructions and execution units are supported—and describe the result as a subset rather than a complete Cray-1.
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Software-capable recreation
A broader goal requires more than arithmetic units. Instruction issue, hazards, vector chaining, memory behavior, interfaces, and software support all matter. Fenton’s documented project was described as binary-compatible and cycle-accurate, but it ran at lower clock rates, used much less memory than the original, and omitted several original features. That makes it a valuable reference, not proof that an equivalent result is a quick or turnkey build.
Use the Cray-1 manuals to define the hardware
Start with the Cray hardware reference and related planning documents in the archived Cray document index. Use them to establish instruction behavior, registers, interfaces, and block structure before writing RTL or committing to an FPGA. A block diagram is a starting map, not a complete implementation specification: control timing and interactions between units need to be worked out and tested.
For context, Fenton’s project documentation describes the original Cray-1 as an 80 MHz design with 12 independent pipelined execution units and vector registers holding 64 values. It gives an original-memory range of 256–4096 kilowords and describes the upper figure as 32 megabytes. These are original-machine specifications, not requirements or achieved capacities for a replica.
Build the FPGA recreation incrementally
Do not begin by trying to reproduce every subsystem at once. The EE Times account of the recreation describes an incremental approach and highlights instruction issuing, hazard detection, vector chaining, and memory as substantial reverse-engineering work.
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Define a testable RTL skeleton
Write down the supported instruction and behavior boundaries. Set up a small top-level design and a repeatable way to test each implemented block before adding the next one.
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Implement address and scalar units
Start with the address and scalar paths, then verify register reads and writes, arithmetic results, and control behavior against the manuals. Keep tests small enough to isolate an error to one unit.
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Add floating-point and vector units
Introduce floating-point operations and vector execution only after the basic scalar and address paths are dependable. Test vector register behavior and the interactions between pipelined units; vector chaining and hazards can affect whether instructions produce the expected results.
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Implement register files, issue, and memory behavior
Integrate the register files and instruction issue/control logic, then test memory access and dependencies between operations. These interactions are central to a faithful recreation, not optional polish.
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Add optional I/O and context switching
Begin with a simple interface such as a UART so you can observe or control the system without first recreating original peripherals. Treat original disk channels and context switching as later extensions.
Fenton’s project account reports an initial operating rate of about 33 MHz, later improved to nearly 50 MHz after multiplier improvements, and about 4 kilowords of memory. The same account says several original features remained absent. These figures describe that particular historical prototype, not a performance target guaranteed on other FPGA boards. The EE Times account characterizes the recreation as about 5,600 lines of Verilog; that reported code size is likewise a description of that project, not a reliable estimate for another implementation.
Choose an FPGA by constraints, not by the historical board name
The documented recreation used a Xilinx Spartan-3E 1600 development board. Fenton’s project documentation suggests that board or an equivalent FPGA platform, but the Spartan-3E 1600 is now difficult to source and catalog listings may be obsolete. Do not assume that a historical part number is currently available or that any board advertised as equivalent will run the design unchanged.
- Logic capacity: Check whether the device can accommodate the RTL you intend to implement.
- Block RAM: Compare available on-chip memory with your design’s storage needs; the historical prototype’s reported 4 kilowords is not the same as the original machine’s memory range.
- Clocking and timing: Confirm that the board and toolchain can support your target clock and that the design meets timing after implementation.
- I/O: Check for accessible pins or interfaces for a simple console connection such as UART.
- Toolchain and board support: Verify that the FPGA tools support the exact device and board before purchase. An older design may need adaptation to a newer part or toolchain.
Buy or borrow a board only after you have checked those constraints against the implementation you plan to build. An FPGA development board is the key electronics platform; it does not remove the work of adapting, compiling, timing, and validating the RTL.
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Scale the enclosure from drawings, not from another model
Find an authoritative Cray drawing, choose a consistent reference point, and multiply each real dimension by 0.1 for a 1:10 model. For example, a measured 100 mm feature on the chosen drawing becomes 10 mm in the model. Keep a dimension sheet and apply the same scale to the frame, panels, base, and settee so that separately fabricated parts fit together.
Do not transfer dimensions from a documented 1:8 model directly to a 1:10 build. Its author described a 1 cm wooden base and 5 mm plexiglass panels and framework, but those are construction choices for that model, not scaled 1:10 specifications. Adapt its cutting approach only after recalculating parts from your source drawing.
Select materials and fabrication methods for the parts
| Part or approach | Documented material or method | How to use it in a 1:10 build |
|---|---|---|
| Frame and body | Fenton’s 1:10 case used MDF and balsa wood, with CNC milling, sanding, paint, and glue. | Use the materials and fabrication method that suit your tools; derive dimensions from a Cray drawing at 0.1 scale. |
| Panels and framework | A documented 1:8 replica used 5 mm plexiglass panels and framework. | Use its fabrication concept as a reference, not its panel thickness or dimensions as a 1:10 specification. |
| Base, lower panels, and “pillows” | The 1:8 replica used a 1 cm wooden base and described a cutting scheme for lower panels and pillows. | Redraw these parts at 1:10 and check their fit against the frame before cutting final material. |
| Seat | Fenton’s case used a pleather couch seat; a separate PicoCray enclosure used a 2 mm laser-cut and engraved foam seat. | Choose a treatment that fits the appearance and scale of your model. The PicoCray seat dimension belongs to that separate enclosure, not a 1:10 Cray-1 specification. |
| Small details and badge | The 1:8 replica used 3D-printed joints and badges, painted plastic tiles, foam pillows, glue, screws, and rubber feet. Its badge was printed at 29-micron layers in Shapeways Frosted Ultra Detail material. | Use printed parts or hand-fabricated substitutes for details. The cited layer setting and material describe that badge job, not a requirement for your printer or service. |
| Alternative enclosure panels | A separate PicoCray enclosure used transparent and red acrylic joined with acrylic welding solution. | Consider acrylic if you want a different enclosure treatment; that example is not a dimensioned 1:10 Cray-1 plan. |
Fenton’s case also used a pleather settee, while the 1:8 model and PicoCray examples demonstrate other ways to fabricate small details and panels. Choose a method you can execute accurately: CNC milling can help with repeatable shaped parts, laser cutting suits flat panels, and hand fabrication can work for a one-off model. Make a test piece before committing expensive material or assembling the finished frame.
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Set the fidelity target
Write down whether the deliverable is a display model, an FPGA subset, or a broader software-capable recreation. For an FPGA build, list the supported units and features; for the enclosure, list which external features you will reproduce.
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Gather the reference material
Read the Cray hardware-reference and planning documents in the archived Cray document index. For the case, locate an authoritative drawing and create your own scaled dimension sheet.
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Prototype the electronics path
Build the RTL skeleton and implement address and scalar units first, followed by floating-point and vector units, register files, issue/control, and memory. Validate each stage before integrating it.
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Verify the FPGA platform
Check logic, block RAM, clocking, I/O, and toolchain compatibility before choosing a board. If the historical Spartan-3E 1600 is unavailable, select another device based on those constraints and expect possible RTL or toolchain adaptation.
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Fabricate the case separately
Cut and assemble the C-shaped frame, panels, and settee independently of the electronics. Dry-fit parts, sand, paint, and add printed or hand-made details before fitting the hardware inside.
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Integrate only after both sides work
Bring the electronics and enclosure together once the board operates reliably and the case dimensions are confirmed. Start external interaction with a simple interface; add harder legacy I/O or software ambitions only when the basic build is stable.
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Plan around the main limitations
- Functional fidelity takes time: The instruction/control interactions and memory system require careful implementation and testing; treating the project as a marathon rather than a sprint is appropriate.
- FPGA resources shape scope: The historical prototype’s clock and memory figures were far below the original machine’s stated specifications, and some original features were left out.
- Legacy software is a separate challenge: The documented recreation lacked several original features, and compatible legacy software is scarce. A running FPGA design should not be confused with a complete software ecosystem.
- Fabrication dimensions are not interchangeable: The available examples include a 1:10 case, a 1:8 model, and a separate PicoCray enclosure. Their materials and techniques can inform your work, but their dimensions cannot be mixed without recalculation.
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