SK hynix’s February 2019 ISSCC presentation detailed a 16Gb DDR5 SDRAM design, not a retail RAM kit. The conference paper title specifies 1.1V operation and a data rate of 6.4Gb/s per pin; the company’s earlier November 2018 announcement instead described a 5200Mbps device. Those figures belong to different announcement and presentation contexts.
What SK hynix presented at ISSCC 2019
The ISSCC 2019 program lists SK hynix paper 23.2, scheduled for February 20, 2019: “A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme.” The title identifies the design’s capacity, process designation, operating voltage and per-pin data rate. ISSCC 2019 Advance Program
This was a technical presentation about a DRAM chip. It should not be read as a specification for a particular desktop or server memory kit.
Reported chip implementation and signal techniques
Die area and process
Contemporaneous coverage by EE Times reported a die area of 76.22 mm² and a 1ynm DRAM process with four metal layers. These implementation details come from that report, rather than the ISSCC paper title. EE Times, February 21, 2019
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Clocking and signal integrity
EE Times reported that the design used a modified delay-locked loop (DLL) combining a phase rotator and an injection-locked oscillator. The approach was described as addressing clock jitter and duty-cycle distortion at higher speeds. The report also identifies write-level training and a modified forward-feedback equalization circuit among the techniques presented.
Why the 2018 and 2019 data rates differ
In its November 2018 announcement, SK hynix described a 16Gb 1Ynm DDR5 device operating at 5200Mbps and 1.1V. The ISSCC paper title published in February 2019 specifies 6.4Gb/s per pin. The two numbers refer to separate company-announcement and conference-presentation contexts; they are not interchangeable specifications for one retail module. SK hynix, November 15, 2018 ISSCC 2019 Advance Program
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The 2018 company announcement also said the device was supplied in RDIMM and UDIMM samples for server and PC platforms. SK hynix compared its stated 5200Mbps rate with 3200Mbps, calling it about 60% faster, and claimed 30% lower power consumption than the DDR4 generation it cited. These are the company’s comparisons, not independent benchmark results.
In an October 2019 company overview, SK hynix said the ISSCC chip could technically support up to 6400Mbps. The same overview described DDR5 as having 32 banks and burst length 16, compared with predecessor figures of 16 banks and burst length 8. These are descriptions from SK hynix, not independent measurements. SK hynix, October 25, 2019
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What the historical production statement meant
In the November 2018 announcement, SK hynix vice president Joohwan Cho said the company planned to begin mass production in 2020, when it then expected the DDR5 market to open. That was a historical company plan, not a current production forecast. The announcement framed the device as meeting JEDEC standards and said samples had been provided to a major chipset maker. SK hynix, November 15, 2018
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.DDR5 chip versus a DDR5 memory module
A DRAM chip is a component used on a memory module. A DDR5 module is the physical product a PC or server owner installs, and it must match the platform. The 2018 announcement’s UDIMM and RDIMM references describe module forms for different system contexts; they do not make the ISSCC chip itself a consumer kit.
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EE Times also reported that Samsung presented LPDDR5 work in the same ISSCC session. LPDDR5 is the low-power variant, not the same chip category as SK hynix’s DDR5 SDRAM. EE Times, February 21, 2019
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