How a 15 MHz-Wide PLL Synthesizer Was Modeled: Part 3

Frederick Weist’s Part 3 models a specific high-frequency PLL synthesizer in its locked, linear condition. The example has a reported 15 MHz loop bandwidth and is evaluated at 22.5, 31.3, and 39.9 GHz. Its closed-loop simulations show less than 2 dB of peaking, according to Weist; these are results for this design, not a general performance guarantee.

What Part 3 models

The model examines the dynamics of a single-loop, high-frequency synthesizer after it has locked. That distinction matters: a locked, linear model is useful for analyzing loop response and stability, but it does not by itself describe the full acquisition process or establish performance under every operating condition.

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Weist uses Keysight Genesys, a general frequency-domain simulator, because he says the filter topology was more complex than specific PLL simulators could accommodate. He describes adjusting the general model to represent the actual synthesizer. The article does not provide enough information here to reproduce the model independently or to treat its results as an independent validation.

Operating points and reported response

The three cases represent the low-band edge, mid-band, and high-band points. Weist reports a 15 MHz loop bandwidth and less than 2 dB of closed-loop peaking in the simulations.

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Weist presents the under-2-dB closed-loop peaking alongside open-loop simulations with good stability margins. These are related but distinct views of the loop: open-loop margins help assess stability, while closed-loop peaking describes the response after feedback is closed. The reported figures belong to this example and its model.

Why the filter uses two paths

The broader design described in Part 2 is a Type 2, second-order PLL with a first-order active proportional-integral (PI) loop filter. It divides filter work between two paths: an op-amp provides the integral path, and a differential proportional amplifier supports the high-frequency proportional path. The series associates this proportional path with enabling the unusually wide loop bandwidth.

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Part 2 gives design targets of 9.677 MHz natural frequency and a damping factor of 0.707, alongside the 15 MHz loop-bandwidth target. These are design parameters for the series’ example, not default values for PLLs generally. Other stated design features include translational feedback for unity closed-loop gain, internal multiplication, and aided acquisition called “window steering.”

Keeping gain consistent across the band

The voltage-controlled oscillator (VCO) gain varies across the operating band. Part 3 says the design compensates for that variation using phase-frequency detector (PFD) gain control, with the aim of keeping open-loop gain constant across the band. The low-, mid-, and high-band model cases therefore help illustrate the design over its intended frequency range rather than at only one operating point.

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What wide bandwidth means for phase noise

The series advances the design thesis that high-frequency PLLs can benefit from wider loop bandwidth to support low phase noise. That is not a promise that increasing bandwidth will improve phase noise in every implementation: actual results depend on the design and its noise sources. Part 3’s reported loop-response results do not provide a complete numerical phase-noise comparison, so they cannot establish a quantitative noise advantage on their own.

Weist’s broader comparison contrasts indirect PLL synthesis with direct mix-multiply-divide synthesis. He argues that direct synthesis can offer the best performance, while the indirect approach described in the series may come close with lower size, weight, power, cost, and complexity. The article presents that as a design position; the material does not establish independent head-to-head measurements.

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How to interpret the result

• Bandwidth: 15 MHz is the reported value for this example, not a universal target.
• Frequency coverage: the model cases are 22.5, 31.3, and 39.9 GHz.
• Response: the article reports less than 2 dB of closed-loop peaking and relates the result to good open-loop stability margins.
• Evidence scope: these are the author’s reported modeling and design results; the available article material does not supply complete numerical phase-noise results or enough detail for a full independent reproduction.

Weist characterizes the general model as imperfect but a useful starting point, saying it “comes fairly close” and, after circuit values are adjusted, “accurately represents performance of the actual synthesizer (EDM unit).”

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Sources and further reading

• Frederick Weist, “How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 3),” Electronic Design, Nov. 3, 2025.
• Frederick Weist, “How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 2),” Electronic Design, Aug. 25, 2025.
• Frederick Weist, “How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 1),” Electronic Design, Aug. 6, 2025.

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