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ARM’s instruction-set architecture (ISA) defines the behavior software can observe; a processor core’s microarchitecture decides how to implement that behavior. Out-of-order (OoO) execution is an internal scheduling technique, not a change to program order. “ARM predication” is also not one feature: A32 supports broad condition-code execution, A64 keeps selected conditional operations, and SVE predicates individual vector lanes.
Three different ideas: ISA, microarchitecture and predication
These terms describe different layers of a processor.
| Layer | What it defines | What it does not define |
|---|---|---|
| Instruction-set architecture (ISA) | Instruction meanings, registers, flags, exceptions, memory rules and the behavior visible to software. | A particular pipeline width, cache design, execution-unit count or scheduling algorithm. |
| Microarchitecture | How one core fetches, decodes, predicts, schedules, executes and retires instructions. | A new programming model; it must preserve the ISA’s architectural behavior. |
| Predication | A family of conditional-execution mechanisms, from condition-code instructions to vector predicates. | A single ARM-wide instruction format that works identically in A32, A64 and SVE. |
Arm’s Armv8-A architectural model is called Simple Sequential Execution (SSE). It asks software developers to reason as if instructions are fetched, decoded and executed one at a time in program order. SSE is an architectural contract, not a claim that hardware has only one instruction in flight.
How can an ARM CPU execute instructions out of order?
The core overlaps work internally
An OoO core can keep many instructions in flight. It decodes instructions, renames registers to remove false dependencies, tracks which operands are ready and issues independent operations to available execution units. A later instruction can therefore finish before an earlier instruction that is waiting for a cache miss or a long arithmetic operation.
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Arm’s illustrative pipeline has fetch and decode/rename/dispatch in order, followed by out-of-order issue and execution. The example directs work to branch, integer, multi-cycle integer, floating-point/ASIMD, load and store resources. That diagram explains one possible design; it is not a blueprint for every Arm processor. Some Arm cores are in-order, while application-class cores commonly use more elaborate OoO machinery.
Architectural results still follow the contract
The processor records dependencies and keeps enough state to retire work without exposing an impossible architectural state. Register results, stores, exceptions and control-flow effects must be presented according to the ISA’s rules, even if the underlying execution completed in a different order. A cache miss can let unrelated arithmetic run ahead, but software cannot rely on that internal order as a new instruction-set feature.
This distinction explains why “out of order” does not mean “the program runs backward.” It describes when operations use execution resources, not a redefinition of the order in which the machine’s architectural effects become visible.
How does ARM predication work?
Predication makes an operation conditional without necessarily using a conventional branch. The exact mechanism depends on the instruction set state or extension.
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A32: condition codes on many instructions
Classic A32 (the 32-bit ARM instruction state) is associated with broad conditional execution. Many instructions can carry a condition code derived from the flags. An instruction whose condition is false is treated as not executed, so a short sequence can avoid a branch.
CMP r0, #0
ADDEQ r1, r1, r2 @ add only when the EQ condition is trueThis style can reduce branches and sometimes code size. It also creates dependencies through the condition flags: a compare must produce flags before dependent conditional instructions can be resolved. On a modern application core, those dependencies may limit scheduling opportunities even when no branch is present.
A64: selected conditional operations, not general predication
A64, the 64-bit Arm instruction state used by AArch64, removed general-purpose predication of arbitrary instructions in the A32 style. It did not remove conditional behavior altogether. Conditional branches, conditional compares and instructions such as CSEL remain available.
CMP x0, #0
CSEL x1, x2, x3, EQ // x1 = x2 if equal, otherwise x3CSEL performs a conditional data selection: it chooses one of two register values. It is not the same as executing an arbitrary instruction only when a condition is true. Consequently, “ARM64 has no predication” is too broad. A precise statement is that A64 dropped general-purpose instruction predication while retaining specific conditional operations.
SVE: predicates control vector elements
Scalable Vector Extension (SVE) uses predicate registers to mark active and inactive vector elements. The predicate applies at lane level, allowing one vector instruction to operate on selected elements while handling the rest according to that instruction’s merging or zeroing behavior.
FMAD z0.s, p0/m, z1.s, z2.sIn the merging form illustrated here, active lanes perform the fused multiply-add and inactive destination lanes remain unmodified. SVE predication is therefore a vector-lane mechanism, not a return to A32-style condition suffixes on arbitrary scalar instructions.
| Mechanism | Conditional granularity | Typical operation | Important qualification |
|---|---|---|---|
| A32 condition execution | Whole instruction | Condition-suffixed arithmetic or load/store instruction | Flags create dependencies; behavior belongs to the classic 32-bit state. |
| A64 conditional operations | Specific scalar operation or control-flow instruction | CSEL, conditional branch, conditional compare |
No general condition suffix for every instruction. |
| SVE predicate | Individual vector elements | Predicated arithmetic such as merging FMAD |
Inactive lanes follow the instruction’s merge or zeroing semantics. |
What is the difference between ARM predication and a branch?
A branch changes control flow: the processor predicts a target and may speculatively fetch one path. Predication keeps control flow linear but makes an operation, value selection or vector lane conditional. They are not interchangeable in every program.
| Consideration | Conditional operation or predication | Conditional branch |
|---|---|---|
| Control flow | Usually remains on one instruction stream. | Selects between paths and depends on branch prediction for best throughput. |
| Work performed | Instructions may still consume issue and execution resources even when their result is discarded or lanes are inactive. | Only the selected path needs to retire, although speculative work can occur on the predicted path. |
| Dependencies | May depend on flags, predicate registers or both input values for a selection. | Depends on branch resolution and predictor accuracy. |
| Side effects | Must use an instruction whose conditional semantics safely handle the operation; masking a value is not equivalent to suppressing an arbitrary store or exception. | Separates code paths, which can make side effects easier to reason about. |
| Best fit | Short scalar selections, flag-based operations or data-parallel work with naturally varying active lanes. | Longer paths, substantial work differences between alternatives or code where prediction is reliable. |
Does ARM64 support predicated instructions?
Yes, but the answer depends on what “predicated” means. A64 provides selected conditional instructions and branches; SVE provides vector predication when the implementation includes that extension. A64 does not provide the broad, arbitrary-instruction condition-code execution associated with A32.
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For scalar code, choose among a branch, a conditional select such as CSEL or another instruction-specific conditional form according to the operation’s semantics. For SVE code, determine which lanes are active and whether the instruction merges inactive destinations or writes zeros. Do not infer behavior from the word “ARM” alone: identify A32, A64 or SVE first.
When is predication faster than a branch?
There is no processor-independent rule. Predication can avoid a mispredicted branch and may reduce code size, but flag or predicate dependencies can constrain scheduling, and executing work whose result is not used can waste resources. A well-predicted branch can be inexpensive and can let the core pursue only the useful path.
Arm guidance has historically suggested considering conditional instructions for sequences of about three instructions or fewer and a branch for longer sequences. That is a dated rule of thumb, not a benchmark result or a guaranteed threshold for current cores. Branch predictors, pipeline width, execution resources, compiler decisions, input distribution and surrounding dependencies all change the outcome.
“The best-performing solution varies between processors as they have different pipeline and branch predictor designs, and it also varies depending on the specific instruction sequence you are using.” — Jacob Bramley, Arm
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For production code, compare representative compiled versions on the actual target processor. Measure realistic input distributions, compiler options and surrounding code rather than counting source-level instructions or assuming that every Arm core schedules them alike.
A practical way to analyze a conditional sequence
- Identify the ISA and extension. Confirm whether the code is A32, A64 or SVE; the available conditional mechanisms differ.
- Describe the control-flow shape. Is the choice a branch, a scalar data selection or lane-level vector masking?
- Map dependencies. Check flag producers, predicate producers, data inputs and independent instructions that could issue while a dependency is pending.
- Check correctness and side effects. Ensure that masking or selecting values does not accidentally perform a load, store, exception-prone operation or other side effect that the branch would have skipped.
- Measure on the target. Use the real core, compiler and optimization options with a workload that reflects actual branch bias and active-lane patterns.
Learning and experimenting without specialized hardware
Hardware is optional for understanding these mechanisms. Arm’s assembly-language guide describes a GCC workflow with a Fixed Virtual Platform (FVP), and it also describes native execution on an AArch64 computer with a 64-bit operating system. Arm’s documented native example was tested on a Raspberry Pi Zero 2 W. Development Studio and FVP models provide additional ways to build and inspect code without owning a board.
A sensible progression is:
- Assemble small A64 examples and inspect the generated instructions.
- Use a simulator or FVP to observe registers, flags and control flow while stepping through conditional operations.
- Run the same code on AArch64 hardware when available, then compare timing and compiler output.
- For SVE, verify the target’s SVE support and test both fully active and partially active predicate patterns.
The setup notes for Arm’s guide were written and tested with Ubuntu 22.04 LTS and Raspberry Pi OS with a 6.1 kernel, so package names, simulator availability and boot details can vary by platform. A board is useful for native execution and device I/O, but it is not required to learn the ISA or the distinction between architectural order and OoO implementation.
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