On October 18, 2017, Samsung announced that its 8LPP (8nm Low Power Plus) FinFET process had completed qualification and was ready for production. Samsung also said production had already commenced, three months ahead of its planned qualification schedule. Compared with 10LPP, the company claimed up to 10% lower power consumption and up to 10% smaller area, positioning 8LPP as a lower-risk, pre-EUV step toward 7nm.
That announcement described a manufacturing platform, not a finished processor or mining ASIC. It established that Samsung considered the process ready for customer production; it did not disclose wafer volumes, yield percentages, pricing, or a named commercial chip.
What Samsung announced
Samsung’s announcement, published on October 18, 2017, said the 8LPP FinFET process had completed qualification and was ready for production. Samsung stated that qualification finished three months ahead of schedule and that 8LPP production had commenced. The primary announcement is available at Samsung’s release.
The release also quoted Qualcomm Senior Vice President RK Chunduru, who described 8LPP as using proven 10nm technology while improving performance and scalability. That comment indicates industry interest, but it does not identify a Qualcomm product or constitute a public commitment to a specific chip.
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What “8LPP” means
8nm-class process generation
The “8” is Samsung’s nominal process-generation label. It is best read as an 8nm-class technology designation, not as a claim that every transistor feature or metal dimension measures exactly 8nm. Node names are generation labels and are not directly comparable across foundries without examining design rules, transistor density, libraries, and operating conditions.
Low Power Plus
“LPP” stands for Low Power Plus, Samsung’s name for a process derivative optimized for a balance of power, performance, and density. The process still belongs to the FinFET family.
FinFET transistor structure
In a FinFET, the transistor channel rises as a three-dimensional fin and the gate controls it from multiple sides. This gives better electrostatic control than older planar transistors and supports continued scaling. Samsung explicitly described 8LPP as an 8nm FinFET process in its announcement.
8LPP versus 10LPP
Samsung presented 8LPP as an optimization of its established 10nm technology rather than a wholly new transistor architecture. Its headline comparison was:
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| Metric | Samsung’s stated 8LPP result versus 10LPP | How to interpret it |
|---|---|---|
| Power consumption | Up to 10% lower | An upper-bound claim that varies with circuit, voltage, frequency, and design implementation |
| Area | Up to 10% smaller | An upper-bound claim; actual die scaling depends on logic, SRAM, analog, I/O, and utilization |
| Scaling mechanism cited | Narrower metal pitch | More wiring density can contribute to a smaller layout |
| Manufacturing basis | Proven 10nm process technology | Reuse of process learning was intended to reduce transition risk |
These figures are not guarantees for every customer design, and they are not necessarily cumulative benefits under identical conditions. A customer might use the process to hold performance constant while reducing power, hold power constant while increasing performance, shrink the die, or balance all three objectives. Samsung did not publish a universal benchmark methodology, design example, or independent measurement with the announcement.
Why a 10nm-derived process mattered
8LPP was an evolutionary scaling step. Samsung’s 2017 foundry roadmap described it as combining innovations from the 10nm family with additional performance and gate-density benefits.
Reusing a production-proven process family can shorten learning cycles and make a yield ramp more predictable than introducing a substantially different device structure and patterning flow at the same time. That does not make qualification equivalent to mature high-volume manufacturing, but it explains why Samsung emphasized production readiness and expected a rapid yield ramp.
What “qualified and ready for production” means
For a foundry, process qualification generally means the manufacturing flow has passed internal readiness and reliability requirements sufficiently for customer production use. The sequence normally looks like this:
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- Process and transistor development.
- Qualification against electrical, reliability, and manufacturing criteria.
- Design-kit, library, and ecosystem enablement.
- Customer design and tape-out.
- Initial or risk production.
- Yield learning and high-volume manufacturing.
Samsung’s statement confirms qualification and commencement of production. It does not establish a specific yield percentage, defect density, wafer-volume target, wafer price, or customer shipment level. A qualified process can therefore coexist with customer chips that are still being designed, validated, or ramped.
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8LPP as the bridge before 7nm EUV
Samsung positioned 8LPP as the most competitive option before its transition to 7nm using extreme ultraviolet (EUV) lithography. In practical terms:
| 8LPP | 7nm roadmap direction |
|---|---|
| 10nm-derived FinFET process | More aggressive scaling associated with EUV adoption |
| Pre-EUV patterning approach | Planned EUV-based generation |
| Emphasis on reuse and ramp confidence | Greater technology transition and execution challenge |
Calling 8LPP a bridge does not make it an interim or disposable technology. A mature derivative can be attractive when schedule, manufacturing risk, IP reuse, and performance-per-dollar matter more than using the newest node.
Target applications
Markets named in 2017
Samsung identified mobile, cryptocurrency, networking, server, and other high-performance applications as targets for 8LPP. The release did not name a mining ASIC, Snapdragon processor, server CPU, or networking chip made on the process.
Why cryptocurrency mining was relevant
For a mining design, a smaller and more power-efficient process could provide more computation per wafer area, lower energy per operation, or better performance within a fixed thermal envelope. However, mining efficiency also depends on architecture, memory bandwidth, voltage, clock speed, physical design, packaging, cooling, and electricity prices. Samsung supplied no mining benchmark.
Current application context
Samsung’s current HPC and AI application material lists 8nm-class technology for selected networking, storage, enterprise, and datacenter categories. Its IoT application material lists 8LPP among supported technologies for areas including camera and surveillance SoCs, machine and robot vision, HMI and media gateways, smart TVs, set-top boxes, wearables, and AIoT accelerators.
Those current tables show intended or supported application categories. They are not a complete historical list of products manufactured on 8LPP, nor do they prove that a particular design is currently accepting orders.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What the announcement did not prove
- It did not announce a finished consumer product.
- It did not identify a named commercial Qualcomm, mining, server, or networking chip.
- It did not publish yield, defect-density, wafer-volume, capacity, or pricing data.
- It did not guarantee that every design would achieve the maximum 10% power or area improvement.
- It did not mean that all production was already mature high-volume manufacturing.
- It did not make 8LPP an EUV process; Samsung positioned it before 7nm EUV.
Why a customer might choose 8LPP
- A mature FinFET family with process learning carried over from 10nm.
- Potentially lower power and smaller area than 10LPP.
- Lower transition risk than moving directly to a newer EUV generation.
- Potentially easier migration for designs based on related 10nm libraries and physical methodologies, subject to Samsung’s actual enablement requirements.
- A suitable performance and cost balance for selected mobile, networking, storage, enterprise, accelerator, and IoT products.
Why a customer might not choose it
- A newer node may justify better density, power, or performance despite higher wafer and design costs.
- “8nm” does not guarantee the same density or performance as another foundry’s differently defined node.
- SRAM, analog, I/O, package, and memory constraints can limit system-level gains even when logic density improves.
- Smaller die area does not automatically mean a cheaper finished chip; mask costs, wafer pricing, yield, packaging, testing, and design effort also matter.
- Migration from 10LPP still requires physical-design changes, timing closure, IP qualification, verification, and potentially new masks.
How 8LPP fits Samsung’s portfolio in 2026
Samsung’s current foundry overview spans mature and advanced technologies, including 14nm, 10nm, 8nm, 5nm, 4nm, and 3nm GAA processes, while its process-technology overview extends the public roadmap through 2nm-class technologies and beyond.
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Bottom line
Samsung’s 2017 announcement meant that 8LPP had passed the company’s process-qualification gates and was being offered for production, with Samsung saying manufacturing had already begun. The technology was a 10nm-derived, pre-EUV FinFET refinement that promised up to 10% lower power and up to 10% smaller area than 10LPP. Its significance was practical rather than revolutionary: incremental scaling, lower transition risk, and production readiness before Samsung’s move to 7nm EUV.
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