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What Synopsys announced
Synopsys’s December 11, 2024 announcement covered silicon IP that chipmakers and system companies can license and integrate into custom designs. The portfolio included PHY IP, controller IP and verification IP; for Ultra Ethernet, Synopsys specified MAC and PCS controller IP, while its UALink offering included a controller. The company also described integration support drawing on its Ethernet and PCIe-related IP.
That distinction matters: the announcement was not a launch of a Synopsys-branded switch, network interface card, accelerator board or complete AI fabric. Synopsys said its existing Ethernet and PCIe IP had supported more than 5,000 successful customer tapeouts; that is the company’s claim about its broader IP history, not evidence of UALink or Ultra Ethernet tapeouts.
Synopsys named AMD, Astera Labs, Juniper Networks, Tenstorrent and XConn as companies collaborating on the ecosystem. Being named as a collaborator indicates engagement, not a commitment by each company to ship a product using this Synopsys IP.
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Why AI systems need faster interconnects
Large AI workloads are spread across multiple accelerators. Their performance depends not just on how quickly each accelerator computes, but also on how efficiently the system moves data, shares or accesses memory, and synchronizes work. If an accelerator spends time waiting for remote data or other devices, its peak compute capability may go unused.
Interconnects address different parts of that problem. A system needs ways to communicate closely among accelerators and ways to move traffic between servers and across a cluster. Those are related requirements, but they are not the same layer of the architecture.
Ultra Ethernet and UALink solve different connectivity problems
| Attribute | Ultra Ethernet | UALink |
|---|---|---|
| Primary role | Scale-out networking across nodes and the cluster fabric | Scale-up communication among accelerators in a tightly coupled system |
| Typical scope | Servers, racks, switches, NICs and cluster connections | Accelerators within an AI pod or similar system |
| Technology family | Ethernet-based networking adapted for AI and HPC workloads | An accelerator-link protocol for high-bandwidth accelerator communication |
| Synopsys IP announced | PHY, MAC/PCS controller and verification IP | PHY, controller and verification IP |
| Announced headline metric | Up to 1.6 Tbps of bandwidth | Up to 200 Gbps per lane |
| Announced scale | Systems scaling to up to one million endpoints | Systems with up to 1,024 accelerators |
| Intended benefit | Scalable cluster networking for AI and HPC | Low-latency, shared-memory-oriented accelerator communication |
The figures in the table are claims in Synopsys’s announcement, not proof that a customer deployment reached those scales or that every design will achieve the headline bandwidth. The two technologies are potentially complementary: a system could use UALink for local accelerator connectivity and Ultra Ethernet for communication across nodes.
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What the Ultra Ethernet numbers do—and do not—mean
Synopsys said its Ultra Ethernet MAC and PCS controller could provide up to 1.6 Tbps of bandwidth, and described a 224G Ethernet PHY, a patented error-correction implementation and interfaces to higher layers of the Ultra Ethernet stack. The 1.6-Tbps figure is an IP capability claim; the announcement does not establish application-level payload throughput in a deployed system.
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Ultra Ethernet is an industry effort to adapt Ethernet for demanding AI and HPC traffic, including concerns such as congestion control, reliability, telemetry and collective communication. It is not simply a faster label for conventional Ethernet. The Ultra Ethernet Consortium develops the broader specification and ecosystem; Synopsys supplies a commercial IP implementation. Ethernet electrical and PHY standards, consortium protocol work, customer silicon and the software and systems stack are related but distinct. Synopsys’s announcement does not mean its IP supplies every layer of an Ultra Ethernet network.
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What UALink is intended to do
UALink—Ultra Accelerator Link—is aimed at scale-up connectivity: communication among accelerators within a closely coupled system. Synopsys described its PHY as supporting up to 200 Gbps per lane and its solution as supporting systems with up to 1,024 accelerators. The announcement does not specify enough about lane aggregation, directionality or protocol overhead to calculate one universal aggregate or usable payload bandwidth.
Synopsys said the controller was designed to support shared-memory access between accelerators and reduce infrastructure bottlenecks. That describes an architectural goal, not a guarantee that every implementation presents one uniform memory pool or provides identical coherency semantics. A design team needs to establish which memory model and operations the applicable UALink revision defines, what is hardware-coherent, what software support is needed, and what ordering, latency and link-recovery behavior the implementation guarantees.
The UALink Consortium is the industry-backed effort behind the open accelerator interconnect. Open-standard positioning can give vendors an alternative to depending exclusively on one proprietary link ecosystem, but it does not by itself establish multi-vendor interoperability. Specification revision, compliance testing, compatible switches and accelerators, and software support all matter.
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Why a combined IP portfolio may matter to chip designers
Obtaining PHY, controller and verification components from one IP supplier can reduce the work of assembling and validating separate blocks, and may help a design team integrate connectivity earlier. Synopsys’s announcement also positioned the products alongside its existing high-speed Ethernet and PCIe IP experience.
A bundle does not remove customer-specific engineering. The chipmaker still has to integrate the blocks with its on-chip network, DMA engines, memory system, security design and firmware; validate the package and signal integrity; and build or integrate software and system management. Verification IP can help check protocol behavior, but cannot prove sustained fabric performance, thermal viability, software correctness, interoperability with every vendor or reliability under failures.
How the announcement compares with other options
| Technology or ecosystem | Where it fits | Key distinction |
|---|---|---|
| NVIDIA NVLink and NVSwitch | Scale-up connectivity in NVIDIA-oriented systems | A tightly integrated NVIDIA hardware and software ecosystem, rather than neutral IP intended for arbitrary chip designers. See NVIDIA NVLink. |
| InfiniBand | Established AI and HPC cluster networking | A deployable specialized networking ecosystem, not the same architectural layer as an accelerator scale-up link. See NVIDIA InfiniBand. |
| Conventional Ethernet | Broadly used network connectivity | Familiar hardware and management ecosystem; highly synchronized AI workloads may need additional mechanisms and tuning. |
| CXL | Memory expansion, pooling and coherency-oriented designs | Its role depends on topology; it is not automatically a one-for-one substitute for either UALink or Ultra Ethernet. See the Compute Express Link Consortium. |
| Proprietary accelerator fabrics | Vendor-optimized accelerator systems | Can tightly couple hardware and software, while potentially increasing dependence on one supplier and limiting interchangeability. |
These are not interchangeable products that can be ranked by headline bandwidth alone. Compare their architectural role, software and management support, ecosystem maturity, and the degree of vendor dependence. A system buyer evaluating a complete cluster has a different decision from a chip designer selecting licensable interface IP.
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What “industry’s first” establishes
Synopsys announced what it called the industry’s first Ultra Ethernet and UALink IP solutions. The cited release establishes that Synopsys made that claim; it is not an independent industry-wide audit showing that no other company had previously offered any related component. Likewise, an IP announcement is not evidence of production silicon, broad adoption or demonstrated interoperability.
Availability: announced schedule versus confirmed deployment
In its December 11, 2024 release, Synopsys scheduled Ultra Ethernet IP availability for the first half of 2025 and UALink IP availability for the second half of 2025. Those were forward-looking dates. That release does not confirm that either product became generally available, identify a public price, or establish customer tapeouts or production deployments. Buyers should confirm current availability, specification revision and licensing terms directly with Synopsys rather than treating the announced schedule as proof of shipping status.
What chipmakers and system buyers should verify
For chip designers considering IP
- Specification maturity: Identify the exact standard revision the IP implements and whether it is final or subject to change.
- Process and packaging support: Confirm supported foundries, nodes, package technologies and any retimer requirements.
- PHY performance: Request signal-integrity, reach, equalization, jitter-tolerance and power data for the intended configuration.
- Controller integration: Check interfaces to the design’s NoC, DMA, memory, security and firmware architecture.
- Verification evidence: Ask about protocol coverage, error injection, formal results, compliance collateral and interoperability testing.
- Software and ecosystem: Establish availability of drivers, runtimes, collective-communication libraries, telemetry and fabric-management support.
- Commercial terms: Obtain license, royalty, customization, maintenance and support details from Synopsys. The announcement publishes no list price or self-service licensing plan.
For system buyers
- Verify that the chosen accelerators, NICs, switches, retimers and cables support compatible revisions and have been tested together.
- Request workload-relevant all-reduce and all-to-all results, effective payload throughput, tail latency, congestion behavior and power per transferred bit.
- Ask how the system handles link failures, recovery and fault isolation, and evaluate orchestration and software support alongside silicon capabilities.
- Assess rack cabling, signal integrity and thermal constraints, as well as how much control remains with one platform vendor.
Protocol compatibility alone does not guarantee plug-and-play operation: lane mapping, clocking, SerDes characteristics, equalization, retimers, package design, cable reach and error-correction behavior can all affect interoperability. A standards-based link still needs system-level validation.
Who should evaluate Synopsys’s offering?
The announcement is most relevant to semiconductor companies, hyperscalers with custom-silicon programs, accelerator vendors, and networking or switching companies that can license and integrate IP into their own designs. It is not an off-the-shelf purchase for an individual developer or an organization seeking a ready-to-install AI cluster. Synopsys describes its DesignWare IP portfolio at Synopsys DesignWare IP; organizations evaluating a license can use the Synopsys contact page to pursue vendor discussions.
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For a silicon program, the practical comparison is not simply Synopsys versus a complete NVIDIA or InfiniBand platform. Compare IP suppliers on the exact standard revision, process-node support, validation evidence and commercial terms; separately assess complete systems if the need is deployed infrastructure. The announcement does not establish that Cadence offers equivalent UALink or Ultra Ethernet IP, so any such comparison requires confirmation of the specific product and revision.
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