For a single-phase grid-connected inverter, calculate a first-pass filter from rated current, switching-ripple limits, capacitor reactive power, inductance voltage drop, and resonance—not from cutoff frequency alone. An LC filter may be adequate in some applications, but grid-connected voltage-source inverters commonly use an LCL filter with inverter-side inductance L1, shunt capacitor Cf, and grid-side inductance L2. The LCL resonance must then be damped and checked against grid-impedance variation and controller bandwidth.
Do not connect an unverified prototype to a live utility. Filter calculations do not establish anti-islanding, protection, power-quality, or interconnection compliance.
LC or LCL: which filter does a grid-connected inverter need?
“LC filter” is often used as the search term, but the technically appropriate topology for many modern grid-tied PWM inverters is LCL. TI’s single-phase reference design uses an LC filter in standalone voltage-source mode and an LCL output filter in grid-connected mode (TI TIDM-HV-1PH-DCAC).
| Criterion | LC | LCL |
|---|---|---|
| Topology | One series inductor and one shunt capacitor | Inverter-side L1, shunt Cf, and grid-side L2 |
| High-frequency attenuation | Approximately −40 dB/decade ideally | Approximately −60 dB/decade ideally |
| Parts and losses | Fewer parts; may require more series inductance | Extra inductor, copper loss, volume, and voltage drop |
| Resonance and control | Strong resonance; grid impedance matters | Resonance is more complex and must be damped |
| Typical use | Some standalone or low-power designs | Common choice for grid-connected PWM converters |
An LCL filter is not automatically better. It normally achieves more switching-ripple attenuation for a given total inductance, but it creates a resonant plant that must be included in the current-control design.
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Design inputs you must define
| Quantity | Symbol | Required specification |
|---|---|---|
| Rated active power | Pn | W |
| Grid RMS voltage | Vg | V RMS, at the filter/PCC |
| Grid frequency | fg | 50 or 60 Hz |
| DC-link voltage | Vdc | V, including minimum and maximum |
| PWM switching frequency | fs | Hz and effective ripple frequency |
| Power factor | PF | Usually near unity, but specify the operating range |
| Allowed inverter-side ripple | ΔiL1,pp | A peak-to-peak or percentage of rated peak current |
| Capacitor reactive-power limit | QC,max | Often specified as a fraction of rated power |
| Maximum inductive voltage drop | — | Percentage of grid voltage |
| Estimated grid inductance | Lg | H, including feeder and transformer |
| Control and sampling frequency | fctrl | Hz, with digital delay |
| PWM method | — | Bipolar, unipolar, or other modulation |
The topology and PWM method are essential: no single ripple equation applies to every bridge, modulation scheme, or definition of switching frequency.
1. Calculate rated grid current
For a single-phase inverter:
Ig,rms = Pn / (Vg PF)
Ig,pk = √2 Ig,rms
At 3 kW, 230 V RMS, and unity power factor:
Ig,rms = 3000/230 = 13.04 A, and Ig,pk = 18.45 A.
Inductors, capacitors, semiconductors, relays, fuses, sensors, conductors, and thermal interfaces must accommodate RMS current, peak current, ripple, overload, and fault transients.
2. Select the shunt capacitor from reactive power
At the grid fundamental frequency, the capacitor draws:
QC = ωgCfVg2, with ωg = 2πfg.
Therefore:
Cf ≤ QC,max/(ωgVg2)
If the limit is xCPn, use Cf ≤ xCPn/(ωgVg2). Published single-phase design procedures commonly use approximately 2.5–5% of rated power as a starting range, not as a universal standard requirement (IET Power Electronics design paper).
For 3 kW, 230 V, 50 Hz, and a 5% limit:
Cf,max = 0.05(3000)/(2π·50·2302) = 90.3 μF.
A provisional 47 μF or 68 μF capacitor must still be checked for fundamental and switching-frequency current, inrush, dv/dt, temperature, lifetime, and transient voltage. Use an AC-rated film capacitor or another component explicitly approved for this service; an ordinary DC electrolytic is not a substitute.
3. Calculate the inverter-side inductor from PWM ripple
L1 is normally selected first because it limits switching ripple and semiconductor current stress. A generic starting relationship is:
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L1 ≥ ΔvL/(2fsΔiL1,pp)
The exact coefficient depends on bridge topology, bipolar or unipolar PWM, modulation index, carrier definition, effective ripple frequency, and operating point. One representative full-bridge procedure uses ΔI1/Iref = Vdc/(4L1fsIref) and discusses ripple choices roughly in the 15–40% range (IET Power Electronics design paper).
- Choose a ripple target, such as 20–30% of rated peak current.
- Determine the worst-case PWM voltage across L1 for the actual modulation.
- Calculate a minimum inductance.
- Verify the switching waveform at minimum and maximum DC-link voltage by simulation and measurement.
- Check saturation at fundamental peak current plus half ripple, overload, and transient current.
For the illustrative 3 kW example, 400 V DC, 20 kHz, and 20% ripple:
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Using the representative equation gives L1 ≥ 400/[4·20,000·3.69] = 1.36 mH. A provisional 1.5 mH part is only a starting value; the actual PWM implementation determines the final result.
4. Basic LC cutoff calculation
For an ideal LC network:
fc = 1/(2π√(LC))
Thus:
L = 1/[(2πfc)2C]
A first pass should satisfy fg ≪ fc ≪ fs, while also leaving adequate control bandwidth and damping margin. There is no universal cutoff ratio.
With 2 kHz, 47 μF:
L = 1/[(2π·2000)2·47 μF] ≈ 134 μH.
This result is not a complete grid-tied design. Check fundamental voltage drop, capacitor reactive current, resonance amplification, attenuation at PWM sidebands, grid impedance, and controller stability.
5. LCL filter calculation
For inverter-side L1, capacitor Cf, and grid-side L2:
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fres = (1/2π)√[(L1+L2)/(L1L2Cf)]
Include upstream grid inductance by replacing the grid-side branch with L2+Lg:
fres = (1/2π)√{[L1+(L2+Lg)]/[L1(L2+Lg)Cf]}
Given L1, Cf, and a target resonance, let K = (2πfres)2Cf. Then:
L2 = L1/(KL1 − 1), valid only when KL1 > 1.
Keep resonance away from the line-frequency and low-order harmonic region, current-loop crossover, sampling and delay artifacts, and switching-frequency sidebands. A published procedure uses a representative range above the line-frequency region and below roughly half the switching frequency; treat that as a starting guideline, not a rule (IET Power Electronics design paper).
Grid-side inductance and voltage drop
The total fundamental-frequency inductive drop is approximately:
VL,rms = ωgLTIg,rms
For an allowed fraction xL of grid voltage:
LT ≤ xLVg/(ωgIg,rms).
Ripple attenuation gives a lower bound on inductance; voltage drop gives an upper bound. The design is viable only when those bounds overlap. A 10% total-inductance drop is a commonly used design constraint, not a mandatory value (published LLCL/LCL design reference).
6. Damping the resonance
Passive damping
A common arrangement places Rd in series with Cf. A starting estimate is:
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Rd ≈ 1/(3ωresCf), where ωres = 2πfres.
Verify resistor RMS and switching-frequency current, pulse energy, continuous dissipation, temperature rise, and tolerance of L1, L2, and Cf. Passive damping is simple but dissipates energy.
Active damping
Active methods emulate a damping resistor in software using capacitor-current or capacitor-voltage feedback, virtual resistance, notch filters, state feedback, or observers. They avoid much of the physical damping loss but require reliable sensing, correct loop polarity and gain, adequate sampling, delay compensation, and stability verification across tolerances. These approaches are discussed in LCL active-damping research and recent active-damping work.
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7. Component and loss checks
Inductors
- Specify RMS, peak, saturation, overload, and transient current.
- Evaluate copper loss, core loss at PWM ripple frequency, skin and proximity effects, DC resistance, and thermal rise.
- Check insulation, creepage, clearance, mechanical mounting, audible noise, and leakage inductance.
A useful design margin is Ipeak,design ≥ Ig,pk + Δipp/2 + overload current + transient current.
Capacitors
The fundamental capacitor current is IC = ωgCfVg, plus switching ripple. Verify AC RMS and peak current, voltage, repetitive pulse current, dv/dt, ESR/ESL, temperature, lifetime, and any self-healing or safety approvals.
Damping resistors and protection
Check continuous and pulse power, fusing, inrush limiting, discharge paths, overcurrent protection, surge protection, contactors, residual-current detection, and safe fault behavior.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.8. Worked 3 kW example
| Assumption | Value |
|---|---|
| Rated power | 3 kW |
| Grid | 230 V RMS, 50 Hz |
| DC link | 400 V |
| Switching frequency | 20 kHz |
| Power factor | 1 |
| Capacitor limit | 5% of rated power |
| Selected capacitor | 47 μF |
| Ripple target | 20% of rated peak current |
- Current: Ig,rms = 13.04 A and Ig,pk = 18.45 A.
- Capacitor: QC = 2π·50·47 μF·2302 ≈ 78 var, or 2.6% of 3 kW. This is below the illustrative 5% limit.
- Inverter-side inductor: ΔiL1,pp = 3.69 A. The representative equation gives 1.36 mH minimum; 1.5 mH may be selected provisionally.
- LCL iteration: At a provisional 4 kHz resonance, 1.5 mH and 47 μF produce a calculated L2 of about 0.072 mH from the ideal equation. That small value may not provide the desired PCC ripple or practical current rating.
The result demonstrates why the values must be iterated. Reduce capacitance, change the L1:L2 split, move the resonance, accept more total inductance, change switching frequency, or consider an LLCL topology. Include grid inductance before freezing the design.
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9. Simulation, measurement, and grid validation
- Linearize the inverter, filter, controller, and grid model; inspect gain and phase margins.
- Sweep minimum, nominal, and maximum grid inductance and resistance.
- Sweep capacitor and inductor tolerances, ESR, ESL, dead time, sampling delay, PWM delay, and sensor noise.
- Simulate minimum and maximum DC-link voltage, modulation index, overload, and grid-voltage distortion.
- Perform low-voltage, current-limited laboratory tests with suitable isolation.
- Measure inverter-side current, capacitor current, PCC voltage, and grid-side current; state the measurement bandwidth and test point.
- Verify thermal rise, saturation, damping-resistor power, inrush, protection, anti-islanding, residual current, overcurrent, and overvoltage functions.
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10. Interconnection standards are a separate requirement
IEEE 1547-2018 covers distributed-energy-resource interconnection and interoperability, including abnormal-condition response, power quality, islanding, testing, and commissioning. It does not prescribe one universal L, C, or LCL filter value. Check the adopted edition, IEEE 1547.1 testing requirements, local utility rules, product certification, and applicable national standards through the IEEE 1547 standard page and IEEE DER ecosystem guidance.
LC, LCL, or another topology?
- Single L filter: simplest control plant and no capacitor resonance, but requires more inductance for equivalent attenuation and can incur greater voltage drop and loss.
- LC: fewer parts and useful in some standalone voltage-source systems, but resonance and grid-impedance sensitivity remain significant.
- LCL: strong switching-frequency attenuation and lower total inductance for many grid-connected designs, at the cost of damping and control complexity.
- LLCL: a specialized resonant branch can target switching harmonics, but design and control are more involved (IET Power Electronics design paper).
- Multilevel or higher-frequency inverter: may reduce filter requirements while increasing semiconductor, gate-drive, control, and protection complexity.
Final design checklist
- Rated RMS and peak current calculated for the actual voltage and power factor.
- Capacitor reactive power and RMS ripple current within specification.
- Ripple equation matched to bridge topology and PWM method.
- Inductor saturation, copper loss, core loss, insulation, and temperature verified.
- LC or LCL resonance calculated with worst-case grid inductance.
- Resonance separated from control bandwidth, line harmonics, and switching sidebands.
- Passive or active damping verified for tolerance and thermal stress.
- Grid-current attenuation and THD measured at the defined PCC, not assumed from an ideal model.
- Dead time, sampling delay, sensor dynamics, and protection included in simulation.
- Low-voltage tests completed before any grid connection.
- IEEE, utility, certification, anti-islanding, and safety requirements separately confirmed.
Frequently Asked Questions
Can I calculate a grid-tied filter using only the LC cutoff formula?
No. The cutoff equation is a first pass. You must also check capacitor reactive power, PWM ripple, voltage drop, resonance, damping, grid impedance, component stress, control stability, and interconnection requirements.
Is an LCL filter always preferable to an LC filter?
No. LCL usually improves switching-ripple attenuation but adds a second inductor, resonance, losses, and control complexity. The topology must match the inverter mode and compliance target.
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One free scan finds every outdated or missing driver and matches the right update for your exact hardware.Free scan · exact hardware matchDoes a calculated filter guarantee IEEE 1547 compliance?
No. IEEE 1547 addresses DER interconnection and interoperability; compliance requires the applicable testing, protection, certification, and utility procedures in addition to filter design.
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