CPUs have used eDRAM, but only in selected designs. IBM used it for large POWER-family caches, and Intel used a separate eDRAM die inside the package in selected Haswell-era processors. The reason it is not a universal replacement for SRAM is that eDRAM can provide far more capacity per area, while SRAM remains better suited to the smallest, most latency-sensitive caches.
Has eDRAM ever been used as CPU cache?
Yes. IBM POWER processors used eDRAM for large caches, and Intel shipped eDRAM in selected Haswell-era packages. These examples show that eDRAM is an engineering option for CPU systems, not a technology absent from processors.
IBM POWER8: large caches alongside SRAM
IBM lists 512 KB of SRAM L2 cache per core and 96 MB of shared on-chip eDRAM L3 cache for POWER8. It also describes up to 128 MB of eDRAM off-chip L4 cache per socket. The mix illustrates a practical division: SRAM for a smaller cache close to each core, and denser eDRAM for much larger cache capacity. IBM’s POWER8 cache overview
Intel Haswell: eDRAM in the package, not on the CPU die
Intel’s documented Haswell implementation placed the eDRAM data store on a discrete die made with Intel’s eDRAM process technology and connected it to the CPU by a high-speed interface. In this case, “embedded” did not mean the memory array was fabricated directly on the CPU logic die; it was a separate die in the same package. Intel’s Haswell architecture paper
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Why isn’t eDRAM used for every cache?
The core tradeoff is capacity per area versus access speed. IBM Research described logic-based eDRAM as holding six to eight times as much memory as SRAM in the same area, a comparison published in 2005. That density can make eDRAM attractive when a design benefits from a large cache. IBM Research’s eDRAM design and technology discussion
But cache levels do different jobs. The smallest, most latency-sensitive structures benefit from SRAM’s speed; using a denser memory does not automatically make those structures better. IBM’s research identifies speed as a longstanding obstacle to using DRAM as cache and examines logic-based eDRAM as a way to address the challenge. The engineering question is therefore not simply which memory stores more bits per area, but whether the added capacity is worth the access characteristics and integration choices for a particular cache level.
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What determines whether a CPU design benefits?
- Cache capacity: eDRAM’s density is most useful when the design can make good use of a substantially larger cache.
- Latency needs: small, latency-critical caches favor SRAM, so eDRAM is not a drop-in replacement at every level.
- Integration: an implementation can put eDRAM on the logic die or on a separate die within the package. Intel’s Haswell example used the latter approach.
- Product and workload: the cache hierarchy and intended system determine whether the capacity advantage is valuable enough to justify the chosen implementation.
The cited examples establish that vendors have used eDRAM in CPU products, and the technical sources support a density-versus-speed explanation for its selective use. They do not establish one universal business decision or single cause for why eDRAM has not appeared in more CPUs.
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