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Both x86 and ARM64 allow a later load to become visible before an earlier store to a different address. That means the classic store-buffering test can produce two zeroes on either architecture, even though it may be harder to observe in a short x86 run. The practical fix is not to add fences everywhere: use the synchronization required by your language and algorithm, and test lock-free code on its deployment architecture.
What store-to-load reordering means
Consider two shared variables, initially zero, and two threads:
Thread 1 Thread 2
X = 1; Y = 1;
r1 = Y; r2 = X;If both loads return zero, each thread has read the other variable before the other thread’s store became visible to it. A single sequentially consistent interleaving that preserves all four operations cannot produce that result. Store buffers make it possible: each processor can continue to its load while its own earlier store is still pending visibility to the other core.
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1Clear out junk files and repair common Windows errors2Fix the driver behind crashes, sound loss and screen glitches3Repair Windows errors before they cause bigger problemsThis is the store-buffering outcome. It is allowed on x86 as well as ARM64; it is not an ARM-only failure. Harrison Guo’s September 6, 2026 article reports that the same code can work in Intel CI and on older developer Macs yet fail on Graviton, illustrating why a bug may appear after an architecture migration. That wording is an example, not an independently verified customer report. Read Guo’s explanation and test setup.
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How x86 and Arm compare
Arm Community’s architecture comparison shows that x86 is more strongly ordered for three basic access pairs, but both architectures allow store-to-load reordering. Arm’s DPDK optimization article provides the comparison and guidance on barriers.
| Earlier access → later access | x86 | Arm |
|---|---|---|
| Load → Load | Reordering not allowed | Reordering allowed |
| Load → Store | Reordering not allowed | Reordering allowed |
| Store → Store | Reordering not allowed | Reordering allowed |
| Store → Load | Reordering allowed | Reordering allowed |
This is an architectural comparison, not a complete rulebook for application code. The programming language’s memory model and the synchronization protocol also matter; a program with a data race or inadequate synchronization is not made correct simply because one processor tends to expose a bug less often.
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Why a short x86 test may miss the result
In Guo’s reported test, the both-zero result appeared in approximately 2.3% of one million iterations without barriers and approximately 1.8% of one million iterations with a compiler barrier only. With a full barrier in each thread, the test observed zero such outcomes in that run. These are author-reported results from one setup, not general rates for x86 or ARM64, and zero observations do not prove that a barrier fixes arbitrary concurrent programs. A repost’s author comment repeats the no-barrier and full-barrier figures but is not an independent replication. See the repost and author comment.
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Observation frequency depends on the test and execution conditions. A short run that never sees the outcome does not show it is forbidden. Likewise, the reported percentages should not be treated as predictions for a production workload.
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Compiler barriers are not CPU barriers
A compiler barrier constrains compiler movement of memory references; by itself, it does not impose hardware ordering. A CPU memory barrier constrains processor-visible ordering according to its defined scope and semantics. The two mechanisms address different layers.
For application code, use the language’s atomic and synchronization facilities rather than relying on a compiler-only barrier or treating volatile as general concurrency synchronization. The right operation and ordering depend on the language and algorithm; the sources here do not establish detailed rules for any particular language.
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Choose synchronization for the protocol, not by reflex
Arm distinguishes barriers by what they guarantee. A DMB orders data accesses within the specified shareability domain. A DSB enforces similar ordering and also prevents further instruction execution until synchronization completes. Arm64 acquire-load and release-store instructions provide implicit ordering semantics that are less restrictive than either DMB or DSB. Arm’s guidance on ordering and barriers cautions that unnecessary barriers can reduce performance.
- Identify the communication protocol and the ordering it requires.
- Use the language-level synchronization primitive that expresses that requirement.
- Use a stronger barrier only when the required guarantee calls for it;
DSB SYis not a universal repair for application concurrency. - Test lock-free code on the architectures where it will run. ARM64 development hardware or an ARM cloud platform can help expose architecture-sensitive assumptions, but testing does not replace correct synchronization.
What Intel’s speculative-store-bypass guidance does—and does not—say
The phrase “the bug Intel was hiding” is provocative, but the evidence does not establish that Intel concealed ordinary store-to-load reordering. Intel’s official document addresses a separate behavior: speculative store bypass. Some Intel processors use memory-disambiguation predictors to let a load execute speculatively before the processor knows whether its address overlaps an older store. If there is an overlap, the load may transiently consume stale data before being re-executed to preserve architectural correctness.
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That transient behavior is a security concern because speculative execution can expose information through side channels. Intel discusses mitigations including process isolation, selective use of LFENCE, and Speculative Store Bypass Disable (SSBD), while noting potential performance effects. This security topic is not proof that Intel hid the architectural store-buffering outcome. Read Intel’s speculative-execution guidance.
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