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The original ESP32 can monitor selected inputs while its main processors are in deep sleep, using a small controller Espressif calls the Ultra Low Power (ULP) coprocessor. It can take limited measurements, check conditions and wake the chip when needed—but it is not a second general-purpose CPU running your application.
What is the ESP32 ULP coprocessor?
On the original ESP32, the ULP coprocessor is a finite state machine (ULP FSM) designed for small monitoring and measurement tasks while the main processors sleep. Espressif describes its purpose and the different ULP types used across the ESP32 family in its ULP overview.
Think of it as a specialized low-power controller, not a hidden application processor. It has a restricted instruction set, a small set of registers and access to selected memory and peripheral registers. It cannot be assumed to run the main program or work with every peripheral.
What can it monitor while the ESP32 sleeps?
Espressif documents original-ESP32 ULP FSM use for measurements with the ADC, the chip’s temperature sensor and external I2C sensors. It can also poll sensor readings, ADC values and GPIO states to decide whether to wake the main system. The exact input and configuration must be supported by the chip and the ULP program.
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- Check an analog threshold: periodically sample an ADC voltage and wake the ESP32 if the reading crosses a set threshold.
- Count pulses: monitor an input and count pulses while the main processors are asleep.
- Poll a sensor: take scheduled readings from a supported external I2C sensor and trigger a wake-up based on the program’s conditions.
These are periodic, purpose-built tasks—not continuous full-speed operation of the main application. See Espressif’s ULP FSM programming guide for the documented examples and programming model.
How does the original ESP32 ULP FSM run?
The main application loads the ULP program into RTC memory and starts it. An RTC slow-clock timer then wakes the FSM at the configured interval. It executes from its entry point until it halts or encounters an illegal instruction, then powers down; the timer can start it again on a later interval.
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Espressif’s guide gives an approximately 133 µs minimum period for its stated default 150 kHz configuration, including startup and shutdown overhead. That is a documented implementation detail for that configuration, not a universal timing guarantee for every chip, clock setting or program.
What are its limits?
The original ESP32 FSM has four 16-bit general-purpose registers and uses 32-bit instructions. It can access 8 KB of RTC slow memory, addressed in 32-bit words, plus selected registers associated with RTC control, RTC I/O and the SAR ADC. These constraints make the ULP suitable for compact monitoring logic rather than a full application. Espressif details the instruction and memory model in its ESP32 ULP instruction set reference.
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Original ESP32 FSM programs are written in assembly or with ESP-IDF macro tooling. Do not assume that an example for another ESP32-family chip uses the same coprocessor, instructions or programming approach.
Which ESP32 chips have which ULP?
“ESP32” names a family, and its members do not all use the same ULP implementation. Espressif’s current overview identifies these types:
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| Chip family | ULP type documented by Espressif | Programming distinction |
|---|---|---|
| ESP32 | ULP FSM | Assembly or ESP-IDF macros |
| ESP32-S2 and ESP32-S3 | ULP FSM and ULP RISC-V | The RISC-V type has a different programming model; Espressif documents C programming with standard GNU tools for ESP32-S2. |
| ESP32-C5, ESP32-C6 and ESP32-P4 | ULP LP Core | Not the original ESP32 FSM; consult the relevant chip documentation for its model and capabilities. |
Only one ULP coprocessor type operates at a time on a given chip, according to Espressif. S2 and S3 can enable both types at compile time and select which to use at runtime. The ESP32-S2 ULP RISC-V guide is specifically about that chip and must not be treated as the original ESP32’s programming guide.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What to check if ULP wake-up does not work
Confirm the exact chip and revision, the ULP type expected by the example, and the relevant RTC peripheral and wake-up configuration. Espressif notes a revision-specific caveat for ESP32 revisions 0 and 1: the referenced ULP wake-up mode is supported only when RTC peripherals are not forced to remain powered on; the RTC peripheral power domain should be set to AUTO. The ESP32 sleep-modes guide describes this qualification.
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How to try it on a development board
- Check the module fitted to the board and confirm that it is an original ESP32 if you are following an original-ESP32 ULP FSM example.
- Choose a documented demonstration, such as pulse counting or ADC threshold polling, and verify that its sensor, GPIO or ADC configuration matches your board and chip.
- Load and start the ULP program from the main application, then configure the RTC timer and the wake-up behavior required by the example.
- Test the wake condition and review the chip revision and RTC power-domain settings if the expected wake-up does not occur.
Espressif’s ESP32-DevKitC V4 guide describes a development board with multiple ESP32 module configurations and I/O brought out for peripheral connections. Check the exact module fitted rather than relying on the board name alone.
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