An intelligent processing unit (IPU) is a specialized processor or accelerator architecture designed for machine-intelligence and AI workloads. The name does not describe one standard design: Graphcore uses it for its tiled processor family, while research papers and patents use it for other architectures. When comparing systems, identify the particular vendor or design.
What does IPU mean?
IPU is expanded as either “Intelligent Processing Unit” or “Intelligence Processing Unit” in the cited material. Graphcore’s patent uses “Intelligence Processing Unit” and says the name denotes the processor’s adaptability to machine-intelligence applications; the ExCALIBUR testbed brochure uses “Intelligent Processing Unit.” The differing expansions and distinct research uses show that IPU is a workload-oriented label, not a formal standard with one universally fixed architecture.
How does a Graphcore IPU work?
Graphcore’s patent describes a processor built from many small processing units called tiles. The tiles are arranged in arrays and linked by an on-chip switching fabric; chips can also connect to a host and to one another. For machine-intelligence workloads, computations can be represented as graphs: nodes perform functions and edges carry values, often tensors. Software maps functions and data exchanges across the tiles. These are features of the described Graphcore design, not requirements for every processor called an IPU.
A separate 2025 patent describes another possible tiled intelligence-processing architecture with local buffers, matrix-multiply accelerators, SIMD units, and network-on-chip routers. Its components can vary or be omitted, so the patent illustrates a possible design rather than defining the IPU category or proving that the described implementation is a deployed product.
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What do IPU specifications describe?
Published numbers apply to specific devices and system configurations; they are not baseline requirements for all IPUs.
| Device or design | Reported details | Source and qualification |
|---|---|---|
| Graphcore MK2 GC200 IPU in the IPU-M2000 | 1,472 processor cores; nearly 9,000 independent parallel program threads; 900 MB of processor memory; 250 teraFLOPS of AI compute at the stated FP16 formats | ExCALIBUR Hardware & Enabling Software Testbeds brochure, 2023; figures are for each IPU in that system. Source |
| Graphcore IPU-M2000 system | Four IPUs and approximately 1 petaFLOP of AI compute | ExCALIBUR Hardware & Enabling Software Testbeds brochure, 2023; system-level description. Source |
| Graphcore MK1 | 1,216 IPU tiles and more than 23 billion transistors | Argonne Leadership Computing Facility report, 2022; historic comparison details, not current product guidance. Source |
| Messaging-based m-IPU proposal | 44.5 mW | Chowdhury and Rahman, 2024; reported simulation result, not measured commercial hardware consumption. Source |
The 2023 ExCALIBUR brochure calls Graphcore’s device “a completely new kind of massively parallel processor, co-designed from the ground up to accelerate machine intelligence.” That is the brochure’s institutional description of the technology, not a universal definition of IPU.
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Are all IPUs Graphcore processors?
No. A 2024 preprint proposes a messaging-based intelligent processing unit, or m-IPU: a runtime-configurable AI accelerator whose compute elements, called Sites, communicate through message passing. The paper categorizes its proposed design as a coarse-grained reconfigurable architecture and reports simulated examples. It is a research proposal, not evidence that the design is a commercial product or that its simulated results were measured on physical hardware. Read the preprint.
Patents also use “intelligence processing unit” for other tiled designs. A patent describes claimed or proposed architectural concepts; by itself, it does not establish that a product is available or validate its performance.
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How should you compare an IPU with a GPU or another accelerator?
The label alone does not establish speed, efficiency, or suitability. Compare the actual systems and the workload they will run:
- Workload and software: Check supported models and frameworks, compiler support, and whether the application needs programming changes. An Argonne report associates Graphcore MK1 with Poplar, PyTorch, and TensorFlow; that listing describes its reported setup, not universal IPU compatibility. See the Argonne report.
- Memory and data movement: Compare local or on-chip memory, host-memory access, and communication among tiles and chips. Capacity alone does not explain how efficiently a workload can keep data near the compute units.
- Precision and throughput: Read the numeric format and configuration attached to a throughput figure. A value reported for a named system and FP16 format is not directly interchangeable with one reported under another precision or setup.
- Scaling and communication: Consider the chip-to-chip topology and how much data the workload must exchange. Parallel compute is useful only when communication and synchronization do not undermine the workload’s needs.
- Evidence quality: Distinguish product or testbed specifications from patent descriptions, simulations, and independently measured comparisons. The cited sources do not establish an apples-to-apples benchmark proving that IPUs generally outperform CPUs, GPUs, or other accelerators.
What is the shortest accurate definition?
An IPU is a specialized processor or accelerator architecture intended for AI or machine-intelligence workloads. The term is used for multiple designs, so specify the vendor or architecture when discussing its features or performance.
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