A linear address space is an ordered range of address values used to identify locations. It is not necessarily a range of installed RAM: some addresses may not currently map to physical memory. In Intel protected-mode terminology, the processor translates a logical address into a linear address; if paging is enabled, paging then translates that linear address toward a physical address.
What a linear address space means
Think of a linear address space as a numbered range. Each address identifies a location within that range, and the addresses have a defined order. Carnegie Mellon University defines it as an ordered set of contiguous non-negative integer addresses in its Virtual Memory: Concepts lecture, dated July 5, 2018.
“Linear” describes the address range, not the physical arrangement of memory. Consecutive linear addresses do not have to refer to consecutive physical addresses. Nor does the existence of an address mean that a byte of RAM is currently backing it.
Where it fits in address translation
In Intel protected-mode terminology, address translation can involve three stages. A logical address contains a segment selector and an offset. The processor uses the selector to find a segment descriptor and forms a linear address. When paging is enabled, the paging mechanism translates that linear address toward a physical address. Intel’s IA-32 programmer’s reference manual describes this terminology and sequence. In the documented IA-32 model, with paging disabled, the linear-to-physical relationship is direct.
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| Address term | Role in the translation |
|---|---|
| Logical address | The input address, including a segment selector and offset in Intel protected mode. |
| Linear address | The address formed after segment translation; paging, if enabled, uses it as its input. |
| Physical address | The address used to locate data in physical memory after the applicable translation. |
This sequence is architecture terminology, not a universal description of every processor or operating system. The relevant stages and names depend on the architecture and memory-management mode.
Linear address space versus virtual address space
“Linear” and “virtual” can overlap in operating-system documentation, but the terms are not interchangeable in every context. The 1992 CTOS Operating System Concepts Manual notes that other documentation also calls a linear address space a virtual address space. Intel’s terminology, by contrast, distinguishes the logical address before the linear stage.
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When reading a particular document, check which translation stage it names. A text may use “virtual address” for the process-visible address range generally, or may distinguish virtual, logical, and linear addresses more narrowly.
Why an address may not correspond to resident RAM
A process can have addresses in its linear address space even when the corresponding pages are not resident in physical memory. Linux kernel documentation explains this distinction in its Process Address Space discussion. Page tables and operating-system memory management determine whether an address currently maps to physical memory. Accessing an address without a usable mapping can require operating-system handling, such as a page fault.
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Address widths and paging layouts depend on the system
A linear address space is not defined by one universal bit width or page-table structure. Those details depend on processor architecture and paging mode. For example, Microsoft’s Physical Address Extension documentation describes x86 PAE as changing linear-address translation from two levels to three. Its example divides the address into fields and uses a 12-bit offset for a 4 KiB page. That field layout belongs to the specific x86 PAE example; it is not a general layout for all linear addresses.
Similarly, historical Linux x86 documentation gives a 3 GiB user / 1 GiB kernel split as an example. That figure is specific to the documented kernel context and should not be treated as a rule for current Linux systems. The Phoenix-RTOS Paging technique and Memory Management Unit documentation provides additional context on MMU translation and page granularity.
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How to interpret the term in a technical document
- Identify the stage being discussed: logical, linear or virtual, or physical.
- Check the processor architecture and paging mode before applying a particular address width or page-table layout.
- Determine whether the text refers to a process’s address range or to a broader kernel or system address range.
- Do not assume every address is mapped to a physical page or currently resident in RAM.
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