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1Clear out junk files and repair common Windows errors2Scan for outdated or missing drivers - takes under a minute3Repair Windows errors before they cause bigger problemsUse unsigned for non-negative numeric vectors, signed for two’s-complement values, and std_logic_vector for uninterpreted bit collections. Both arithmetic types come from IEEE numeric_std; a std_logic_vector does not become numeric merely because that package is imported.
This distinction controls interpretation, comparisons, extension, overflow, and whether an expression compiles. The examples below use portable VHDL style and show where explicit conversion or widening is required.
The three vector types
| Type | Meaning | Typical use |
|---|---|---|
std_logic_vector |
No inherent numeric meaning | Raw buses, packed protocol fields, compatibility interfaces |
unsigned |
Non-negative binary integer | Counters, addresses, lengths, masks |
signed |
Two’s-complement integer | Offsets, differences, coefficients, signed samples |
VHDL is strongly typed: signedness is part of the type, not a property inferred from the most-significant bit. A signal cannot be both types without an explicit conversion. The IEEE package declaration defines SIGNED and UNSIGNED as arrays of STD_LOGIC, with the leftmost element as the most-significant bit (IEEE numeric_std declaration).
Representation and ranges
UNSIGNED
An unsigned(N-1 downto 0) value is the sum of each bit multiplied by its power of two. An 8-bit value ranges from 0 through 255: "00000101" is 5 and "11111111" is 255.
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SIGNED
signed uses two’s complement. An N-bit value ranges from -2**(N-1) through 2**(N-1)-1; 8 bits therefore represent −128 through +127. The same pattern "11111111" is 255 as unsigned but −1 as signed. Representation details are documented in the numeric_std package body.
Use numeric_std as the arithmetic baseline
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;The package supplies arithmetic, comparisons, multiplication, division, conversion functions, and resize for signed and unsigned vectors (package declarations). Avoid importing std_logic_arith, std_logic_unsigned, or std_logic_signed into new code: legacy Synopsys packages may be needed for old projects, but competing overloads commonly cause ambiguity. AMD lists both legacy compatibility packages and IEEE numeric_std separately in its Vivado 2026.1 synthesis documentation.
Conversions: reinterpretation versus resizing
Between vectors
u_value <= unsigned(slv_value);
s_value <= signed(slv_value);
slv_value <= std_logic_vector(u_value);These conversions preserve the bit pattern and change its language-level interpretation (or expose it as a general-purpose vector). They do not change width. For example, bits "11111111" become 255 when converted to unsigned and −1 when converted to signed.
Between integers and vectors
u_value <= to_unsigned(integer_value, u_value'length);
s_value <= to_signed(integer_value, s_value'length);
integer_value <= to_integer(u_value);
integer_value <= to_integer(s_value);to_unsigned requires a non-negative integer and an explicit width; to_signed takes an integer and width. to_integer(unsigned) returns a NATURAL, while the signed overload returns an INTEGER. Integer ranges are finite and implementation-dependent, so these conversions are often best kept to control logic or testbenches rather than large datapaths.
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Changing width with resize
wide_u <= resize(narrow_u, wide_u'length);
wide_s <= resize(narrow_s, wide_s'length);Widening an unsigned value adds zeroes; widening a signed value sign-extends by copying its sign bit. Narrowing discards upper bits and can lose information. A cast such as signed(bus) does not perform this width change.
Arithmetic and result widths
Carry-preserving addition
For addition and subtraction, numeric_std operators generally return the larger operand width; they do not automatically create a carry bit for an equal-width destination. Widen before the operation:
signal a, b : unsigned(7 downto 0);
signal sum9 : unsigned(8 downto 0);
sum9 <= resize(a, sum9'length) + resize(b, sum9'length);The same rule applies to signed values:
signal x, y : signed(7 downto 0);
signal sum_ext : signed(8 downto 0);
sum_ext <= resize(x, sum_ext'length) + resize(y, sum_ext'length);Multiplication and accumulation
A full product commonly needs the sum of operand widths:
signal a, b : unsigned(7 downto 0);
signal product : unsigned(15 downto 0);
product <= a * b;For accumulators, choose a destination width that covers the required mathematical range, widen every operand to that width, and document whether eventual truncation is intentional.
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Wrap, truncate, flag, or saturate
Fixed-width arithmetic does not automatically saturate. Assignment to a narrower vector discards bits; modulo wrap may be correct for a counter but wrong for a sensor or audio path. Saturation and overflow flags must be coded explicitly, for example by comparing a widened sum with a limit before assigning the final width.
Mixed signedness, comparisons, and literals
Keep one arithmetic domain
Do not rely on implicit conversion between signed and unsigned. First decide what the bits mean, then convert and resize into a common width:
result <= resize(a, result'length)
+ signed(resize(b, result'length));This is valid only if b’s bit pattern is intentionally being interpreted as signed. If it is a non-negative magnitude, redesign the expression around an appropriate common representation instead.
Comparisons
Relational operators use the operand type’s interpretation. The pattern "11111111" compares as 255 in an unsigned expression and −1 in a signed expression. Convert both operands deliberately before comparing values from different domains.
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Literals
5is an integer literal; contextual overload resolution often makescount + 1clear.x"05"is a based bit-pattern literal whose type still needs context."00000101"is a string literal, not automatically numeric.to_unsigned(5, count'length)andto_signed(-3, offset'length)state width and interpretation explicitly.- A qualified expression such as
unsigned'(x"F0")supplies the required type context.
Complete coding patterns
Unsigned counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
port (clk : in std_logic; reset : in std_logic; q : out unsigned(7 downto 0));
end entity;
architecture rtl of counter is
signal count : unsigned(7 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
count <= (others => '0');
else
count <= count + 1;
end if;
end if;
end process;
q <= count;
end architecture;Raw bus at an interface
signal data_bus : std_logic_vector(15 downto 0);
signal sample : signed(15 downto 0);
sample <= signed(data_bus);
data_bus <= std_logic_vector(sample);Array direction and ports
Descending ranges such as unsigned(7 downto 0) are conventional. Ascending ranges are legal, but consistency matters: vector(0) is not universally the least-significant bit, and conversions do not normalize every range assumption. Check directions when connecting records, arrays, and positional port associations.
Use numeric types directly on ports when the interface is conceptually numeric and the surrounding design supports them. Keep std_logic_vector for raw protocols, fields with multiple interpretations, or compatibility boundaries; convert once at that boundary rather than casting throughout internal arithmetic.
Unknown values and verification
Because these types contain STD_LOGIC, simulation can include 'U', 'X', 'W', 'Z', and '-'. Uninitialized operands can propagate unknowns, and to_integer on invalid bits can warn or fail to yield a meaningful value. Do not conceal initialization bugs by converting everything to integers. Assert reset, range, sign, and width assumptions; where supported by the simulator, an assertion such as assert not is_x(std_logic_vector(count)) can detect unknown values. Verify the exact is_x availability in the imported logic package and tool.
Common errors and fixes
| Symptom | Likely cause | Fix |
|---|---|---|
std_logic_vector + integer fails |
The vector has no numeric meaning | Convert to unsigned/signed, preferably keeping the internal signal numeric |
| Eight-bit sum loses carry | Operands were not widened | resize both operands before addition |
11111111 becomes −1 |
It was interpreted as signed | Choose the intended domain explicitly |
| Negative value becomes a large positive | Zero-extension or unsigned conversion was used | Sign-extend with resize(signed_value, wider_length) |
| Operator is ambiguous | Conflicting packages, mixed types, or an under-specified literal | Remove legacy imports, qualify literals, and use typed intermediates |
| Simulation shows warnings or X values | Missing reset or unknown stimulus | Inspect waveforms, initialize/reset signals, and add assertions |
Alternatives and tool support
numeric_bit offers similar arithmetic using BIT rather than multi-valued STD_LOGIC. VHDL-2008 packages such as numeric_std_unsigned can provide unsigned-style operations on std_logic_vector, but availability depends on the language mode and tool; consult the IEEE 2008 source. For fractional hardware, IEEE fixed_pkg is often clearer than hand-managed scaling; AMD lists it and float_pkg among supported packages.
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GHDL defaults to VHDL-93 unless another standard is selected, and its compatibility options are documented at GHDL invocation documentation. VHDL-2019 is an active IEEE standard (IEEE 1076-2019), but feature support remains tool- and version-dependent; check AMD or Intel matrices, including Intel’s VHDL-2019 support page.
Which simulator or FPGA suite do you need?
- GHDL: free and suitable for learning, command-line simulation, CI, and regression tests; it does not replace vendor synthesis, timing, IP, or programming flows.
- AMD Vivado: appropriate when targeting AMD/Xilinx devices. Its 2026.1 licensing page lists BASIC at $0 with annual renewal, paid CORE and PRO subscriptions, and perpetual ENTERPRISE and GOLD tiers; prices and device eligibility are time-sensitive (official pricing).
- Intel Quartus Prime Lite: a free download with no license file required for supported device families (edition overview).
- Questa Intel FPGA Starter Edition: free but requires a zero-cost license (Intel licensing FAQ).
You do not need a commercial simulator merely to learn signed and unsigned conversions. Start with GHDL; move to Vivado or Quartus when the target FPGA and vendor workflow require it.
Frequently Asked Questions
Is std_logic_vector unsigned in VHDL?
No. It is a collection of logic values with no inherent numeric interpretation. Convert it explicitly to unsigned or signed before arithmetic.
Does VHDL addition automatically keep a carry bit?
Not generally. Widen both operands with resize before addition when the carry must be preserved.
Should new projects use Synopsys arithmetic packages?
Prefer IEEE numeric_std for new portable code. Legacy packages remain useful when maintaining existing designs but can create overload conflicts.
The Bottom Line
Choose the type from the value’s meaning, keep arithmetic in one signedness domain, widen before operations whose full range matters, and convert only at deliberate interfaces.
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