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To use memory more effectively in an NPU, map each workload’s data reuse to the hardware’s storage and data paths. Keep reusable values close to the processing elements (PEs), choose tiles that fit available local memory, and schedule transfers so data arrives when computation needs it. The best arrangement depends on the model, precision, target NPU, and its bandwidth and buffer limits; no single memory size or dataflow is best for every design.

Why memory movement can limit an NPU

An NPU’s compute array can only stay busy when data reaches it at a sufficient rate. Moving weights, activations, coefficients, and intermediate results consumes bandwidth and energy; repeated trips to external memory can constrain performance even when the array has unused arithmetic capacity.

Locality is therefore an architectural feature, not just a compiler setting. Depending on the design, values may be held in PE registers, tile-local memories, or on-chip buffers and scratchpads. These levels reduce the distance data travels and can make reuse possible, but they have finite capacity and bandwidth. A mapping that fits the buffer can still stall if its ports, array interface, or interconnect cannot supply values quickly enough.

Start with the workload’s reuse

Identify the operators and tensors in the target model, then ask how often each value can serve multiple calculations before it must be fetched again. Weights may be reused across output positions; convolution coefficients can be shared across windows; activations may feed neighboring tiles or successive operations; and partial sums may remain local while outputs accumulate. The answer varies with operator, tensor shape, precision, and mapping.

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AMD’s Versal guide gives symmetric FIRs, CNNs, and beamforming as examples of functions with reuse, including shared coefficients and weights. Broadcast or window-based delivery can exploit such sharing when the array and interconnect support it. A dataflow that is effective for one operator may be a poor fit for another, so map the actual workload rather than assuming all tensors should follow the same path.

Map reusable data to the closest suitable storage

  1. Characterize the tensors. Record the relevant weights, activations, partial sums, and intermediate tensors, along with their dimensions, precision, and reuse across output elements, tiles, or operations.
  2. Choose what stays local. Prioritize values with substantial reuse for registers, tile memory, or scratchpad storage, as appropriate to the target architecture. Include partial results and intermediate tensors in the storage estimate, not just model weights.
  3. Size the tile to the real limits. Check whether the working set fits the available local memory and whether the memory’s ports and bandwidth can sustain the required reads and writes. If it does not fit, consider smaller tiles or a different dataflow, then account for the additional transfers those choices create.
  4. Plan the complete transfer path. Trace data from external memory through system interconnects, staging buffers, array interfaces, and tile-local memories. Include communication between tiles as well as transfers into the array.
  5. Overlap transfers and computation where supported. Use the target architecture’s DMA or other scheduled-transfer facilities to stage the next data while current work runs, if the design permits it. Check whether contention or dependencies prevent the intended overlap.
  6. Compare candidate mappings on the target. Evaluate latency, sustained utilization, bandwidth demand, storage footprint, and power with the actual model and platform. A peak compute figure alone does not show whether data supply is the bottleneck.

Consider the entire memory path, not just capacity

External-memory bandwidth, staging-memory capacity, the interface to the array, tile-local storage, and internal communication form one connected constraint. A large buffer cannot compensate for an undersized link; a fast external interface cannot help if the array interface or inter-tile path becomes the bottleneck. Likewise, a compact tile may reduce storage pressure but require more frequent data movement.

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AMD describes its XDNA architecture as a tiled array of AI Engine processors and documents dedicated DMA engines and scheduled transfers among AI Engine tiles. That is one platform-specific example of treating data movement as part of the architecture. For a concrete Versal adaptive SoC example, AMD’s 2026.1 planning guide reports approximately 34 GB/s of LPDDR bandwidth per memory controller to the NoC in the described context. The guide says direct DDR-to-NoC-to-AI-Engine communication is possible but offers lower overall bandwidth, and recommends staging through programmable-logic (PL) memory in many cases before transfer into the array. These figures and recommendations apply to the described Versal context, not to NPUs generally.

Read platform memory figures in context

The same AMD guide describes each Versal AI Engine tile as having eight 4 KB data-memory banks, totaling 32 KB, and local access to three neighboring tiles’ memories, for 128 KB of local shared memory per tile. It gives the VC1902 as an example with 400 tiles and 12.8 MB of total AI Engine array memory. These platform-family figures illustrate how local capacity and connectivity can work together; they are not universal NPU sizing targets.

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When comparing conventional digital NPUs, examine local register and scratchpad capacity alongside external bandwidth, array connectivity, supported data types, and workload reuse. Systolic or other PE arrays can use distributed registers and local partial sums to reduce off-chip traffic, yet a memory-bound workload can still leave the array underused if external bandwidth is insufficient.

When compute-in-memory may be worth considering

Near-memory and compute-in-memory (CIM) approaches place computation closer to storage to reduce movement between separate compute and memory. Resistive RAM (RRAM)-based CIM is one research direction, not a general substitute for conventional NPU memory design. Compare achievable bandwidth and movement reduction against arithmetic throughput, flexibility across models, accuracy, and device and circuit constraints.

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A 2022 Nature study describes NeuRRAM as a 48-core RRAM-CIM research chip containing 3 million RRAM devices. The authors report hardware-measured accuracy of 99.0% on MNIST, 85.7% on CIFAR-10, and 84.7% on Google speech command recognition for the study’s tasks and chip configuration. Those results demonstrate a research approach; they do not predict accuracy or efficiency for other models or hardware.

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How to tell whether a mapping is better

Compare candidate mappings under the same target workload and platform assumptions. Measure end-to-end latency and sustained utilization, and estimate or measure bandwidth demand, local-memory footprint, and power. Trace stalls and traffic across the whole data path so you can distinguish a compute limit from a memory-capacity, bandwidth, or interconnect limit. A mapping that improves reuse may still lose if its tiling increases transfers or exceeds local bandwidth; the target implementation decides the trade-off.

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AMD’s XDNA page describes the AI Engine processor as capable of running at over 1.3 GHz. This is vendor architecture information for that platform, not a general NPU clock target or a measure of application performance. Clock rate should be interpreted alongside the actual data supply and mapping.

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