Yes—but the reported instructions, udbgrd and udbgwr, are not ordinary x86 features for reading or changing microcode. Researchers demonstrated them in a special Intel processor debug state called Red Unlock, where they could access internal hardware interfaces and microcode sequencer arrays. The finding concerns specific Intel platforms and a difficult-to-reach debug mode, not all x86 processors.
What the researchers found
Mark Ermolov, Dmitry Sklyarov, and Maxim Goryachy reported two undocumented instructions while analyzing Intel Atom microcode. Their article appeared online on August 25, 2022, and in a 2023 journal volume. The instructions are named udbgrd (read) and udbgwr (write). Later technical work by Czerny and coauthors describes how, on a Red-Unlocked CPU, they can access internal components exposed through Intel’s Control Register Bus (CRBUS) and Local Data Access Test Port (LDAT), including microcode sequencer arrays.
“Undocumented” here means the instructions are not part of the ordinary publicly documented x86 programming interface. It does not mean that a regular application can simply execute them to inspect or edit a processor’s microcode.
How microcode access works
On the Intel architectures studied, some complex x86 instructions are decoded into micro-operations and handled with help from a microcode sequencer. The sequencer uses internal arrays. The USENIX WOOT 2023 paper discusses a read-only microcode store, or MSROM, writable patch space called MSRAM, and redirection hooks through which patches can change the handling of instructions. Access to those arrays can therefore reveal or alter low-level processor behavior. These details describe the studied Intel architecture, not a universal design rule for every x86 CPU.
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The paper describes CRBUS as an internal bus connecting CPU units and LDAT as a debug interface used for post-silicon validation. In Red Unlock, those interfaces can be reached through JTAG. The undocumented instructions provide software access to internal components exposed through CRBUS and LDAT in that state.
For scale, the paper reports that Goldmont CPUs have space for 7,936 microcode triads in MSROM and 128 triads in MSRAM. Those are figures for the studied Goldmont context; they are not general x86 capacities.
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Why this is not a routine way to read or rewrite a CPU
Red Unlock is a special processor debug state, not a normal operating mode. The USENIX paper says the only publicly known route to achieving it required exploiting an Intel Management Engine vulnerability that had since been patched. The researchers said the method was feasible on Intel system-on-chip CPUs and had been achieved on a small number of devices. They also reported porting their proof of concept to Skylake and Kaby Lake, but in that context it unlocked the Management Engine rather than the CPU.
- Demonstrated CPU families: the public Red Unlock demonstrations discussed in the paper were on Intel Goldmont and Goldmont Plus.
- Not established: universal access across Intel processors, access on AMD processors using these same instructions, or routine access on current systems.
- Hardware caveat: a USB JTAG cable or proprietary debug probe is only a category of equipment used for debug access. A cable by itself does not provide Red Unlock or establish compatibility with a particular board.
Debug access versus official microcode updates
Intel’s documented microcode-loading procedures are a separate, vendor-managed mechanism. Updates may be delivered through the Firmware Interface Table (FIT), BIOS, early operating-system loading, or—in some circumstances—at runtime. Intel recommends loading updates early, before the operating system caches CPU feature enumeration or starts user applications and virtual machines. Runtime loading requires coordinated synchronization across logical processors.
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| Mechanism | Access path | Purpose and scope | Source basis |
|---|---|---|---|
| Documented microcode update | FIT, BIOS, early OS, or supported runtime procedure | Apply vendor-provided security fixes and functional updates through platform maintenance procedures | Intel microcode loading guidance and Intel’s microcode update repository |
| Red Unlock debug access | Special debug state; the reported route involved JTAG access and exploitation of a patched vulnerability | Inspect or modify internal hardware state, including sequencer arrays, on specific unlocked Intel platforms | Ermolov, Sklyarov, and Goryachy; Czerny et al., USENIX WOOT 2023 |
For Linux systems, Intel recommends obtaining processor microcode updates through the operating-system vendor’s update mechanism. That maintenance path should not be confused with using debug interfaces and undocumented instructions to reach internal processor structures.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How the AMD microcode issue differs
AMD’s CVE-2024-36347 is a separate security issue, not evidence that AMD processors expose Intel’s udbgrd and udbgwr instructions. AMD’s bulletin describes a weakness in CPU ROM microcode-patch signature verification that could let a local attacker with administrator privileges load a malicious patch. AMD assigns the issue a CVSS score of 6.4 (Medium), lists affected products and mitigation firmware versions, and advises customers to contact their system OEM for a product-specific BIOS update. The bulletin says AMD had received no reports of the attack occurring in any system.
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