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System Management Mode (SMM) is a special processor mode used by system firmware to handle system-wide work, such as power management and hardware control. On Intel processors, a system management interrupt (SMI) triggers entry into SMM; firmware runs an SMI handler in a protected memory environment, then uses the RSM instruction to restore the interrupted processor state and resume execution.
How SMM, SMI, SMRAM and RSM fit together
These terms describe different parts of one process. Intel’s architecture manuals provide the technical details for Intel 64 and IA-32 processors.
- SMM is the processor mode in which system firmware handles certain system-wide tasks.
- SMI is the system management interrupt that causes the processor to enter SMM. It operates separately from ordinary interrupts and exceptions.
- SMRAM is the memory region used for the SMI handler’s code, data and saved processor state.
- RSM is the instruction the handler executes to leave SMM and restore the interrupted state.
Intel describes SMM as a special-purpose mode for functions such as power management, system hardware control and proprietary OEM-designed code. Ordinary applications and general-purpose operating-system software do not run in SMM. Intel’s Volume 3C architecture manual is the primary reference for this behavior.
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What happens when an SMI occurs?
- The processor receives an SMI. Intel characterizes it as a nonmaskable external interrupt that is separate from the normal interrupt and exception mechanisms.
- The processor reaches a safe transition point. It completes instruction retirement and outstanding stores before switching to the SMI handler.
- The processor saves its context in SMRAM. The handler then runs in SMM’s separate execution environment.
- The firmware handles the requested work. The details depend on the system’s firmware and the SMI source.
- The handler executes RSM. Intel documents RSM as the way to exit SMM: it reloads the saved state and returns control to the interrupted program.
Intel describes SMM as non-reentrant: the processor does not service nested SMIs while it is already in SMM. The exact implementation and firmware tasks vary by platform. For the architectural sequence, see Intel’s Volume 3C manual sections on SMM entry and exit.
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What “transparent” means—and what it does not
SMM is designed to be transparent to the software it interrupts: the processor saves the interrupted context and restores it when the handler finishes. The interrupted program can continue from its saved state, but “transparent” does not mean that SMM is an operating-system feature or a guarantee that firmware is secure.
SMM’s separation and privilege make its firmware code security-sensitive. Intel says SMRAM is typically sequestered DRAM isolated from host DRAM, but a particular computer’s memory protections and firmware configuration cannot be inferred from that general description. Intel discusses this context in its host firmware security guidance.
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What execution environment does Intel SMM use?
On Intel processors, the initial SMM environment has paging disabled and begins in real-address mode. In that initial environment, the handler can address up to 4 GiB. A handler can switch modes while remaining in SMM. These are architectural details, not a promise that every processor architecture or firmware implementation behaves identically; consult the applicable processor documentation for a specific system.
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Intel describes two treatments for SMIs in systems using VMX virtualization. They differ in how SMM interacts with the virtual-machine monitor, and support for the second approach depends on the processor.
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| Intel-documented approach | What happens | Availability |
|---|---|---|
| Default SMI handling | System firmware handles the SMI, then resumes VMX operation. | Described as the default treatment in Intel’s documentation. |
| Dual-monitor treatment | An executive monitor operates outside SMM, while an SMM-transfer monitor operates inside SMM. | Not supported on all Intel processors. |
These are Intel’s documented virtualization treatments, not a general description of every processor vendor’s design. See Intel Volume 3C for the architecture details.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Where to find the architectural reference
For Intel-specific behavior, consult Chapter 32 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C. Intel’s manuals page, updated September 21, 2026, identifies the current manuals: Manuals for Intel® 64 and IA-32 Architectures.
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