The Tool Desk
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Choose the timer function that matches the job
| Goal | Timer function | What it does |
|---|---|---|
| Measure an incoming signal | Input capture | Latches a counter value when a selected input edge occurs; use captured timestamps to calculate period, frequency, or pulse width. |
| Generate a repeating waveform | PWM output compare | Compares the counter with ARR and CCRx to set the period and duty cycle, then repeats while the timer runs. |
| Generate a triggered, bounded waveform | OPM plus output compare/PWM | Starts in response to a configured trigger and clears the counter enable at an update event, allowing an output waveform to stop after a pulse or configured sequence. |
ST describes input capture, output compare, PWM, and one-pulse mode as distinct general-purpose timer functions in its AN4013 timer overview. OPM is not itself a substitute for PWM: combine it with an output channel when the timer must drive a pulse. The trigger and output channel must both be supported and correctly routed by the selected timer.
Calculate the timer clock before choosing register values
Timer timing follows the timer’s actual input clock, prescaler, counting mode, and counter values—not automatically the CPU core clock. Clock-tree rules differ among STM32 families, so identify the clock feeding the particular timer in the MCU’s clock documentation before calculating a period.
For a basic up-counting timer, the counter frequency is fCNT = fTIM / (PSC + 1). With edge-aligned counting from zero through ARR, one PWM period spans ARR + 1 counter ticks, so period = (ARR + 1) / fCNT and frequency = fCNT / (ARR + 1). These expressions assume that the timer is configured for that basic up-counting arrangement; center-aligned modes and timer-specific behavior need their own interpretation.
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In ordinary PWM operation, ARR sets the count range and CCRx sets the compare point that determines the active portion of the cycle. In a common edge-aligned, up-counting PWM setup, the approximate duty ratio is CCRx / (ARR + 1), subject to the selected PWM mode, output polarity, and endpoint behavior. Check the chosen timer’s reference manual for the exact behavior at boundary values.
For example, ST’s AN4776 uses a 1 MHz counter clock in an STM32F302 example. That is an example configuration, not a default STM32 timer clock or a value to copy to another MCU.
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Configure a continuous PWM output
A reliable setup order is to establish the clock and timing first, then configure the channel and enable the timer. ST’s AN4013 setup sequence covers the period in ARR, duty-cycle compare in CCRx, PWM mode and polarity, preload, counting mode, channel enable, and counter enable.
- Confirm the hardware route. Select a timer instance and channel supported by the target MCU, then confirm the chosen package pin has that channel’s alternate function. Check whether the desired output polarity and any complementary output are available on that timer.
- Find the timer input clock. Use the target part’s clock-tree documentation to determine
fTIM; do not assume it equals the core clock. - Choose the counter rate and prescaler. Set PSC to divide the timer input clock to a counter rate that gives sufficient timing resolution and a practical ARR range.
- Choose the counting mode and period. For basic edge-aligned up-counting, calculate ARR from the desired frequency using
ARR = fCNT / fPWM - 1, then check that the value fits the timer’s counter width. Center-aligned counting changes the relationship between the count range and waveform period. - Set duty and output behavior. Program CCRx for the desired compare point, select PWM mode and output polarity, and enable the channel. The pin’s electrical active level depends on polarity as well as the selected PWM mode.
- Consider preload before runtime updates. Preload can keep period or compare changes from taking effect partway through a cycle. Follow the reference manual’s rules for transferring buffered values at update events.
- Enable the channel and counter. Set the relevant capture-compare enable and counter-enable controls, then verify the signal at the configured pin.
The exact register sequence and HAL calls depend on the MCU, timer, and software package. ST’s STM32C5xx HAL TIM documentation, version 2.0.0, describes that HAL’s timer API and usage for the C5xx series; it should not be treated as a universal HAL reference for every STM32 family. For direct register setup or another HAL family, use documentation for the target device and package.
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Use OPM for a triggered pulse
In triggered OPM, one timer input or routed trigger starts the counter, while an output channel generates the waveform. Configure the output compare channel for PWM1 or PWM2, set the delay and pulse width through the appropriate compare and auto-reload values, and enable OPM so the counter stops when the relevant update event occurs. ST’s AN4013 gives a register-level sequence and timing expressions for its described configuration; AN4776 explains OPM behavior and update-event considerations. Treat these as configuration examples, not family-neutral register recipes.
- Select a valid trigger path. Choose an input or internal trigger supported by the timer’s slave-mode controller, and configure the trigger routing and slave trigger mode for that timer.
- Configure the output channel. Set the chosen channel to PWM1 or PWM2, configure polarity, and assign its output to the intended alternate-function pin.
- Program the timing. Use the timer’s counter clock and prescaler to convert the required delay and pulse width into counter ticks. Set the compare and auto-reload values according to the chosen PWM mode and the timer’s documented counting behavior.
- Enable one-pulse behavior and check update handling. Configure OPM and ensure update events are not masked in a way that prevents the expected stop behavior. Update-event handling affects when the counter stops and how buffered values transfer.
- Arm and test the trigger. Enable the relevant output and timer controls in the order required by the device, apply the trigger, and confirm the output timing at the pin.
For a device-specific example, ST’s STM32G4 RM0440 reference manual specifies the pre-trigger OPM condition CNT < CCRx ≤ ARR, including a nonzero CCRx. This is an STM32G4 constraint from that manual, not a universal rule for all STM32 timers. Check the corresponding section of the exact target part’s reference manual before selecting compare values.
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Measure a signal with input capture
Input capture records the timer counter when a configured edge arrives at a channel. To measure period, capture timestamps on successive like edges and subtract them, accounting for counter rollover. To measure high time, capture a rising edge and the following falling edge; to calculate duty cycle, compare that high time with the period measured across matching edges.
- Route the input. Verify the timer channel and pin alternate function, then configure the input polarity and any input filtering or prescaling appropriate to the signal.
- Set the timer time base. Choose the input clock and prescaler to balance resolution against the maximum interval that can be measured before rollover.
- Capture the required edges. Configure a channel for the needed edge or edges. If separate captures or channels are used for opposite edges, confirm that arrangement is supported by the timer.
- Calculate elapsed ticks. Subtract the earlier captured count from the later one. For a single rollover on an up-counter with ARR as its top value, the elapsed ticks are
(ARR + 1 - earlier) + later; if no rollover occurred, uselater - earlier. Handle multiple rollovers separately if the event interval can exceed one counter cycle. - Convert ticks to time. Divide elapsed ticks by the configured counter frequency. Frequency is the reciprocal of the measured period, and duty percentage is
high time / period × 100.
Very short or irregular signals may require input filtering, overflow accounting, or interrupt/DMA handling, depending on the required measurement rate and timer capability. Check the exact timer’s capture, filtering, and channel-routing limits in its reference manual.
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Generate a finite train of pulses
Some STM32 timers can use a repetition counter with OPM to produce a finite pulse train. In the N-pulse method described by ST’s AN4776, the repetition count is set to N − 1; update-event handling is part of the method. Repetition counters are not present on every timer peripheral, so first confirm that the selected timer has one and follow the family-specific instructions. Do not assume that setting OPM alone will produce an arbitrary number of pulses.
Quick Recap
Check compatibility before adopting a configuration
- Timer features: Confirm counter width, channel count, repetition-counter availability, complementary outputs, and synchronization features for the exact timer instance.
- Trigger routing: Verify that the desired trigger source can reach that timer and that the selected slave mode is supported.
- Clock and range: Check the timer input clock, prescaler range, ARR/CCRx range, and whether the required timing resolution fits the counter.
- Counting and update behavior: Distinguish edge-aligned from center-aligned operation, and confirm how preload and update events affect the output and OPM stop point.
- Pin and polarity: Check the package-specific alternate-function table and configure active-high or active-low behavior as required by the connected circuit.
- Software layer: Use the reference manual and HAL documentation for the selected STM32 family; examples from another series may use different timer features, labels, or clock assumptions.
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