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Spin Transfer Technologies (STT) and Tokyo Electron (TEL) announced a collaborative engineering program in October 2017 to develop spin-transfer MRAM (ST-MRAM) for SRAM- and DRAM-class applications. STT contributed perpendicular magnetic tunnel-junction (pMTJ) design and device-fabrication know-how; TEL brought MRAM deposition equipment and magnetic-film formation expertise. The announcement described development goals, not a commercial product or production launch.

What did STT and TEL work on together?

The companies said they would combine STT’s pMTJ device technology with TEL’s deposition capabilities to develop denser, faster, higher-endurance ST-MRAM. A pMTJ is the magnetic storage element at the heart of this type of MRAM; forming its thin magnetic films consistently is one part of making the device manufacturable.

TEL’s development material identifies a wider set of process modules for STT-MRAM, including magnetic and metal physical vapor deposition (PVD), magnetic annealing, cleaning, etch and chemical vapor deposition (CVD), and oxide/nitride CVD. It names imec and Tohoku University among its development partners. These materials describe TEL’s broader MRAM process work and should not be read as proof that every listed module was part of the specific STT agreement.

What did each company contribute?

Partner Contribution described in the October 2017 announcement Why it mattered to the development goal
Spin Transfer Technologies High-speed, high-endurance pMTJ design and device-fabrication technology Provided the device architecture and fabrication know-how the program sought to advance.
Tokyo Electron An ST-MRAM deposition tool and expertise in forming magnetic films Addressed deposition and materials formation, key process steps for building magnetic memory devices.

The announcement framed the collaboration as engineering development: bringing device design and process equipment expertise together. It does not specify a jointly released tool, a qualified production process, or a finished memory chip.

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What performance and size targets did TEL describe?

TEL said the partners were pursuing pMTJs below 30 nm and described them as 40–50% smaller than other commercial solutions. Those are targets and comparisons in TEL’s 2017 announcement, not independently reported measurements of a product that reached market. The announcement also set out broader ambitions for improvements in speed, density, and endurance.

The stated application path began with replacing embedded SRAM, with DRAM replacement presented as a longer-term possibility. ST-MRAM is nonvolatile, so it can retain data without power. But the announcement noted that further gains in switching speed and endurance were needed to match or exceed SRAM.

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What related manufacturing work was reported in 2018?

A May 14, 2018 Tohoku University release described work by its CIES consortium and TEL on reactive-ion-etching processes and 300 mm-wafer integration for high-capacity STT-MRAM. The release reported high performance and improved rewrite tolerance and yield, and presented the work as a step toward practical manufacturing.

This is related process-integration evidence, not confirmation that the 2017 STT–TEL engineering program produced those results. It also does not establish that a particular STT–TEL process entered production.

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Was the STT–TEL partnership commercialized?

The available announcements and technical material do not establish whether the specific 2017 program remained active, reached volume production, or resulted in a commercial memory product by 2026. The evidence supports describing it as a collaborative engineering program with stated device and process goals; it does not support a claim that those goals became a qualified commercial product.

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