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On SM120, a dependent machine instruction can safely use a producer’s register result only when the target instruction sequence gives the result enough time to become available. A community reverse-engineering project reports that scheduling metadata controls this delay and that an encoded delay that is too short can expose stale register data. That is a project finding—not a guarantee in NVIDIA’s PTX specification.
What result visibility means for an instruction dependency
Here, “result visibility” means that a producer instruction has made its register result available to a later, dependent instruction in the same thread. If the consumer reads the register before that result is ready, it may use an older value instead.
This is different from visibility in PTX’s memory model. NVIDIA’s Parallel Thread Execution ISA, version 9.4 uses communication order to describe visibility among overlapping memory operations. That formal memory relationship does not specify when a machine-code register result is ready for a dependent consumer.
The distinction matters because PTX is a virtual ISA: PTX code is translated into the target hardware’s instruction set. A property of generated machine-code scheduling is therefore not automatically a PTX-language guarantee.
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What the SM120 report claims
The community reverse-engineering project basalt, by sunnypatell and contributors, reports that fixed-latency instruction dependencies on SM120 rely on scheduling metadata in machine instructions. In the project’s account, if the encoded delay is too short, a consumer can read stale register contents without a fault or warning.
This describes a potential correctness problem in the generated machine-code sequence, not PTX’s memory-consistency rules. The project’s claim should be attributed to its reverse-engineering work; the consulted NVIDIA PTX references do not publish it as an SM120 scheduling specification.
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What the available measurements establish
Architecture support is not a latency guarantee
NVIDIA’s PTX ISA 8.7 added support for sm_120 and sm_120a. That establishes PTX support for those targets in that ISA version; it does not establish fixed-latency scheduling behavior for every machine instruction.
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The cited hardware scope is one card
In a Reddit post dated August 24, 2026, the project author describes measurements on one GeForce RTX 5070 Ti. The author cautions that SM120 results should not be carried over to SM100 just because both architectures are part of Blackwell. One card’s measurements also do not establish identical behavior across every SM120 GPU.
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Instruction latency figures are observations
The separate community reference SM_120 Microarch Reference lists fma.rn.f32 as mapping to FFMA with a measured four-cycle latency. Treat that as a characterization from that source, not an NVIDIA-published guarantee or a universal latency rule for all instructions, dependency patterns, or GPUs.
Which artifact should you inspect?
Read PTX for the virtual-ISA operation
PTX helps identify the operation and dependency expressed at the virtual-ISA level. Use it to understand what the compiler is being asked to implement, but do not infer from PTX alone that a particular target-machine scheduling delay is encoded or sufficient.
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Inspect generated machine code for target scheduling
If the question is whether a dependent instruction has enough delay on SM120, the relevant evidence is the generated target machine code and its scheduling metadata. Check the producer, the consumer that depends on its result, and the metadata governing their separation. A PTX listing cannot substitute for this inspection when the claim concerns lower-level scheduling control.
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Hardware measurements can test a specific instruction and dependency on a specific GPU. They do not, by themselves, establish behavior on another architecture or every card in the same architecture family. The cited basalt report names an RTX 5070 Ti as its measurement card; it is an example of the reported setup, not a required purchase.
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How to assess an SM120 fixed-latency claim
When evaluating a report, check these details before applying its conclusion:
- Target: Is the result for SM120, SM100, or another architecture?
- Hardware: Which GPU model was measured, and how many models are represented?
- Dependency: Which producer and consumer instructions were tested, and do they have the same register dependency you care about?
- Latency: Is the delay a measured value or an assumption? Which instruction and conditions does it cover?
- Artifact: Was the claim derived from PTX, inspected target machine code, or a hardware measurement?
- Authority: Is it an official specification or a community experiment?
Readers seeking the concept do not need a GPU. Reproducing the cited kind of hardware measurement requires an SM120 GPU and suitable low-level tooling; the available report does not establish that its findings apply to every SM120 card.
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