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Most CMOS differential-amplifier failures come from interacting limits—not one bad transistor. Start by checking the DC bias point and input common-mode range; then isolate gain, CMRR, offset, noise, swing, speed, and stability with the right simulations. This guide focuses on the MOS differential pair and OTA, with separate notes for fully differential circuits and resistor-based difference amplifiers.
Which CMOS differential amplifier are you designing?
“CMOS differential amplifier” can describe several circuits with different failure modes. The main discussion here is the transistor-level MOS differential pair or operational transconductance amplifier (OTA).
- NMOS input pair: Often useful when the input common-mode voltage is not close to the lower supply rail. Its lower input limit depends on the tail-source and input-pair headroom.
- PMOS input pair: Can support lower input common-mode voltages, with different headroom and noise trade-offs.
- Resistive-loaded pair: Straightforward, but resistor load and supply headroom affect gain and swing.
- Active-current-mirror-loaded pair or five-transistor OTA: Compact and potentially low power; finite output resistance and limited output swing can constrain gain and range.
- Telescopic or folded-cascode amplifier: Cascoding can raise output resistance and gain. A telescopic stack uses substantial headroom; a folded cascode trades some simplicity for a different headroom arrangement.
- Fully differential amplifier: Has two signal outputs and needs common-mode feedback (CMFB) to control their average voltage.
- Source-degenerated or precision front end: Source degeneration can improve linearity at the expense of gain and headroom. Chopping or auto-zeroing can address low-frequency offset and noise, with added switching complexity.
A resistor-based difference amplifier is not the same circuit as a MOS differential pair. In the former, resistor-ratio matching often sets a major part of CMRR; in an integrated transistor pair, device matching, current-source behavior, topology, and layout are central.
How the differential pair works—and what its simple equations leave out
For the input voltages, define differential input and common-mode input as:
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vid = vin+ − vin−vicm = (vin+ + vin−)/2
With a matched pair and balanced inputs, a tail current IT is approximately divided equally: each branch carries about IT/2. For a small differential input, the output-current difference is approximately iod ≈ gmvid, where gm is the input-device transconductance. A first-order gain estimate is Av ≈ gmRout.
These are small-signal estimates, not guarantees. The useful gain depends on the effective output resistance, loading, operating region, and frequency. Real short-channel devices, body effect, parasitics, and mismatch matter. A large differential input also steers most of the tail current into one side, so the pair is no longer in its small-signal linear range. Increasing gm alone cannot fix inadequate output resistance, headroom, or stability.
Set the specifications before sizing devices
Write down the conditions the design must meet. A circuit can meet a gain target at one bias point and still be unusable at the intended input common mode, load, temperature, or output swing.
- Supply voltage and allowed supply variation.
- Input common-mode range and differential input range.
- Differential gain, CMRR, and PSRR, including the frequencies at which they apply.
- Bandwidth or unity-gain frequency, phase margin, slew rate, and settling accuracy.
- Output common-mode voltage, output swing, and load capacitance.
- Input-referred thermal and flicker noise over the signal bandwidth.
- Input-referred offset, drift, power, and area limits.
- Process, voltage, temperature, and load corners, plus the required mismatch yield.
First diagnostic: is the DC operating point valid?
Run a DC operating-point analysis before interpreting AC gain or transient response. For every MOSFET, inspect its operating region, VGS, VDS, VDSAT or overdrive as defined by the model, drain current, and terminal voltages. Confirm that current mirrors have compliance and that intended current-source devices retain enough VDS to operate as current sources.
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- Low gain or an output near a rail: Check saturation, bias voltages, load, and current-mirror compliance before changing device sizes.
- Unequal branch currents at nominally equal inputs: Verify the input voltages are actually equal; then inspect mirror ratios, device polarity and bulk connections, mismatch, and layout asymmetry.
- Operating point changes sharply with input common mode: Sweep common mode and identify which transistor first loses its intended operating region.
Common-mode range and output swing: the headroom limits
In an NMOS-input pair with an NMOS tail source, the low end of input common mode must leave room for the tail source and the input pair’s gate-to-source voltage, with enough margin for the devices to operate as intended. The high end must preserve voltage across the input devices and active loads. For a PMOS-input pair, the corresponding constraints shift toward the opposite rail.
There is no universal input-range number: thresholds, overdrive, body effect, topology, load, process corner, temperature, and required output swing all affect it. Derive the limits from the relevant operating-region conditions, then sweep the input common-mode voltage in simulation across PVT. Low supply voltage makes stacked input, tail, cascode, and load devices especially difficult to accommodate; a Berkeley CMOS design report discusses limited supply headroom as a major analog-design constraint in scaled CMOS: Berkeley EECS technical report.
Input range and output swing are coupled: a pair can accept the input common mode yet clip when the requested differential signal moves one output too close to a rail. In a single-ended-to-differential or fully differential path, check input common mode, output common mode, and any level shifting together. Analog Devices’ design tips discusses source impedance matching, input common-mode limits, and level shifting as related design considerations.
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- If a stacked topology fails swing, consider fewer stacked devices, a different input-pair polarity, or a folded rather than telescopic cascode.
- Reducing overdrive may recover headroom, but can affect speed and variation; evaluate it against the actual process models.
- Rail-to-rail inputs can extend the common-mode range, but complementary input pairs may introduce crossover behavior, offset changes, and extra capacitance.
Common problems, symptoms, and corrective actions
Gain is lower than expected
The estimate Av ≈ gmRout assumes an appropriate small-signal operating point and an effective output resistance that the real circuit may not provide. Short-channel effects can reduce intrinsic gain; finite output resistance, output loading, a low-resistance mirror, parasitic capacitance, or a device leaving saturation can lower measured gain further. See CMOS amplifier background; for a specific design, rely on its process models and design documentation rather than a generic gain claim.
- Increase channel length where the speed and area trade-off is acceptable.
- Use cascoding or gain boosting if the supply allows the headroom and the additional poles are manageable.
- Reduce output loading, or distribute required gain across stages if the application permits.
- Recheck gain with the intended load and extracted parasitics, not only an unloaded schematic.
CMRR is poor or common-mode input creates output error
Common-mode rejection is the ratio of differential gain to common-mode gain: CMRR = |Ad/Acm|; in decibels, CMRRdB = 20 log10|Ad/Acm|. The definition is also used in Analog Devices’ differential-amplifier material.
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A finite tail-source output resistance lets common-mode input changes modulate total pair current. Device and load mismatch, mirror-ratio error, unequal parasitic capacitances, supply or substrate coupling, asymmetric routing, and CMFB imperfections can convert common-mode signal into differential output error. Measure differential and common-mode gain separately at a specified frequency, common-mode voltage, load, and operating condition; CMRR is not a frequency-independent promise.
- Raise tail-source output resistance, for example with cascoding where headroom permits.
- Match input and load devices, mirror ratios, orientation, surroundings, and routing.
- Check CMRR over frequency and across the valid input common-mode range. A measurement outside that range is not meaningful; see Analog Devices’ CMRR guidance.
In a resistor-based difference amplifier, ratio mismatch can dominate even if the op amp itself is ideal. TI analyzes resistor-ratio effects in SBOA422 and SBOA582. As an example under its stated assumptions, Analog Devices reports that a unity-gain difference amplifier with 1% resistors can have approximately 34 dB CMRR, versus approximately 54 dB with 0.1% resistors. Those figures describe that example, not every circuit or resistor set.
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Input offset is the differential input required to bring the output to its nominal zero or common-mode condition. Random threshold-voltage, transconductance, geometry, and current mismatch contribute; systematic layout gradients, unequal routing or source/drain resistance, thermal gradients, and bias-reference error can contribute as well. Distinguish random mismatch from systematic mismatch, and check whether offset changes with common mode, temperature, supply, or frequency.
Larger matched input devices often reduce random mismatch, but increase area and gate capacitance and will not correct a systematic asymmetry. Layout, trimming, chopping, or auto-zeroing may be appropriate depending on the offset budget and acceptable complexity. CMOS can offer very low input bias current, while offset, drift, CMRR, and PSRR trade-offs depend on architecture and operating conditions; Analog Devices discusses these precision trade-offs.
Noise exceeds the budget
Analyze input-referred noise at the actual operating point, over the application’s signal bandwidth and source impedance. Contributors can include input-pair channel thermal noise, tail source, active load, bias reference, resistors, and following stages. At low frequencies, flicker noise may matter strongly; larger device area generally reduces its input-referred contribution, at the cost of area and capacitance.
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Increasing transconductance can reduce the input pair’s thermal-noise contribution in suitable operating regimes, but usually costs current or device capacitance. Common-mode supply, substrate, clock, or digital interference can also emerge as differential error when coupling is asymmetric. Do not treat a single noise density as a complete result: integrate over the relevant bandwidth and include source impedance and downstream noise.
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The differential pair is approximately linear only around small differential input. As the input grows, it steers most of the tail current into one branch, causing gain compression, distortion, unequal output slew, clipping, or slow recovery from overload. Source degeneration can improve linearity and extend useful input range, but lowers gain and adds resistor noise and headroom requirements. Feedback, reduced signal amplitude, or a different front-end architecture may be better if the linearity target is strict.
Bandwidth, settling, or stability fails
Relevant poles may occur at the output, high-impedance mirror node, cascode nodes, input nodes, CMFB nodes, or in package, routing, and load capacitances. Wider devices can add transconductance but also capacitance; longer channels may improve output resistance while affecting speed and area. Check the actual loaded circuit and extracted layout.
Fully differential designs have both differential-mode and common-mode feedback behavior to verify. A CMFB loop that is too slow, unstable, incorrectly polarized, or out of range can allow output common mode to drift or saturate even when differential gain appears correct. Examine loop stability and settling for both modes.
Slew rate or overload recovery is poor
As a first-order estimate, slew rate is SR ≈ Iavailable/Cload. The available current and capacitance depend on topology, compensation, wiring, device parasitics, and external load; positive and negative transitions may differ. Test step response, startup, common-mode steps, large differential inputs, and recovery after output saturation or an input outside its valid range.
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PSRR or bias sensitivity is poor
Supply variation can alter tail current, input-pair transconductance, active-load current, output common mode, offset, CMRR, and pole locations through mirrors and bias generators. Run PSRR analysis or inject supply noise at the relevant rails; differential symmetry by itself does not guarantee supply-noise rejection.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Fully differential circuits need a working CMFB loop
A fully differential amplifier controls two outputs, but the differential path alone does not determine their average voltage. Common-mode feedback senses output common mode and drives the circuit toward a reference VOCM. Without effective CMFB, both outputs can move together toward a rail while their difference still appears plausible.
Verify the output-common-mode sensing, reference, CMFB amplifier polarity and range, common-mode loop gain, bandwidth, and phase margin. Check how differential loading affects sensing, and test startup and common-mode recovery. Ensure the CMFB control output can supply the required bias range without interfering with the differential signal path.
A practical SPICE and verification workflow
- Do hand analysis: Estimate bias currents, saturation constraints, common-mode range, output swing, gain, and power from the chosen topology.
- Run nominal DC operating point: Check device regions, currents, node voltages, branch balance, mirror compliance, and CMFB bias.
- Sweep DC conditions: Sweep input common mode, differential input, output common mode, and load to find where operating regions or swing fail.
- Run AC analysis: Measure differential gain and common-mode gain separately; derive CMRR, PSRR, bandwidth, and phase margin under the intended loading.
- Run transient analysis: Test small and large steps, slew in both directions, settling, startup, overload recovery, and common-mode response.
- Run noise analysis: Calculate input-referred noise over the actual bandwidth and source impedance.
- Check PVT corners: Include process, supply, temperature, and load extremes relevant to the product.
- Run Monte Carlo: Separate process variation and mismatch where the simulator supports it; measure input-referred offset and specification yield.
- Repeat with post-layout extraction: Re-run DC, AC, transient, noise, corners, and mismatch tests with extracted parasitics.
- Report margin and yield: A nominal pass is not evidence that the design meets its specification across variation.
If transient behavior looks acceptable but AC analysis does not, confirm that the circuit is linearized at the intended operating point, AC sources excite the correct differential or common-mode signal, neither source nor node is floating, and CMFB is enabled and biased. If gain collapses after layout, inspect extracted output capacitance, mirror-node parasitics, routing resistance, clock coupling, device surroundings, and any post-layout operating-point shift.
Layout and mismatch: what schematic simulation cannot show
Matched devices should see matched physical conditions. Use common-centroid placement and interdigitation where appropriate, dummy devices at array edges, consistent orientation and surroundings, and balanced routing resistance and parasitic capacitance. Keep well, guard-ring, and substrate environments symmetric; isolate sensitive nodes from digital or clock coupling; and route differential signals with matched paths and appropriate shielding.
When Monte Carlo offset is worse than expected, check device area and mismatch model assumptions, mirror mismatch, bias-circuit mismatch, systematic layout effects, and whether output error has been correctly referred back to the input. Random mismatch simulations do not automatically capture every systematic layout gradient or coupling mechanism.
Choose a fix by the failing specification
| Design goal | Common remedy | Cost or risk |
|---|---|---|
| Higher gain | Longer channels, cascoding, gain boosting, or another gain stage | Headroom, speed, area, or additional poles |
| Higher bandwidth | More bias current, smaller devices, or lower node resistance | Power, gain, noise, or mismatch trade-offs |
| Better CMRR | Higher tail-source resistance, better matching, cascoding, symmetric layout | Headroom and area; swing may fall |
| Lower offset | Larger devices, careful layout, trimming, chopping, or auto-zeroing | Capacitance, area, ripple, or complexity |
| Lower thermal noise | Increase transconductance or optimize current density | Power and input capacitance |
| Lower flicker noise | Increase area, consider a PMOS input pair, or use chopping | Area, capacitance, or switching artifacts |
| Wider input common-mode range | Complementary rail-to-rail input pairs or level shifting | Crossover distortion, offset variation, or added capacitance |
| Wider output swing | Reduce stacked devices or use a different cascode arrangement | Potentially lower gain or more complex biasing |
| Better linearity | Source degeneration, feedback, or a linearized input stage | Lower gain, resistor noise, or headroom |
| Lower power | Reduce current or use weak-inversion operation where suitable | Speed, slew rate, or variability |
When the circuit needs a different architecture
If the specification cannot be met simultaneously for input range, gain, swing, noise, and power, revisit the topology rather than endlessly resizing one pair. A five-transistor OTA may be adequate for a modest-gain, low-power stage; a cascode or second stage may be needed for more gain; a fully differential path can provide differential swing but adds CMFB; and a resistor-based difference amplifier may suit board-level sensing where resistor-ratio accuracy dominates. Make the choice against the full specification and verify it under the intended operating conditions.
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