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Open-source processor cores can be credible starting points for IoT hardware, but a CPU core alone is not a ready-to-deploy connected device. For a small control-oriented design, compare Ibex; for optional DSP-style extensions and an OpenHW integration example, evaluate CV32E40P and CORE-V-MCU; for a configurable VHDL microcontroller-like system with software infrastructure, consider NEORV32. The right choice depends on the required instruction set, system components, implementation target, license, and evidence for your exact configuration—not on a universal “best IoT core.”
What “ready for IoT” means
A processor core executes instructions. An IoT product also needs a surrounding system: memory, clocks and reset, interrupts, peripherals, startup software and drivers, debug access, and an appropriate network or radio subsystem. Security, update strategy, manufacturing, and product lifecycle requirements also sit at the system level. A project that supplies more of these pieces can reduce integration work, but its listed peripherals do not by themselves establish that it is a complete network-connected product.
Start by deciding which kind of starting point you need:
- Reusable CPU RTL: a processor block to integrate into a custom SoC.
- Reference subsystem: a processor packaged with memory and peripherals for integration or FPGA prototyping.
- Physical device: a manufactured chip or development board that can be programmed. This is a different deliverable from open-source RTL, and a supported FPGA configuration does not guarantee that every design will build on a particular board.
Open-source processor options at a glance
| Design | What the cited project documentation describes | Useful fit | Important qualification |
|---|---|---|---|
| Ibex | PULP describes a 2-stage, 32-bit, area-optimized control core implementing RV32-IMC. | Investigating a compact control-oriented core. | This is a project characterization, not a normalized current silicon benchmark. [PULP implementation page] |
| CV32E40P | OpenHW’s v1.1.0 user manual describes a 4-stage, in-order, 32-bit RISC-V core. Its standard base is RV32I, with compressed instructions, integer multiply/divide, counters, CSR operations, and instruction-fetch fence support; optional FPU and CORE-V/PULP extensions are described. | Evaluating a synthesizable core with optional capabilities and a documented OpenHW integration path. | The manual says FPGA synthesis is supported, while describing ASICs as the primary design target; a target-technology clock-gating module must be supplied. [OpenHW CV32E40P user manual] |
| CORE-V-MCU | An OpenHW reference system using CV32E40P v1.0.0, an embedded FPGA resource, 512 KB on-chip SRAM, and peripherals including UART, QSPI, I2C, SDIO, camera, GPIO, PWM timer, and JTAG. | Examining a more complete subsystem and documented FPGA or ASIC configurations. | The overview cautions that only its listed peripheral set and physical implementations are known to build properly. [OpenHW CORE-V-MCU overview] |
| NEORV32 | A platform-independent VHDL RISC-V design providing a configurable CPU, SoC, software framework, and test infrastructure, with optional memories, timers, serial interfaces, GPIO, external bus, bootloader, and JTAG-accessible debugging. | Starting with a self-contained, configurable MCU-like system rather than a standalone CPU IP block. | The project describes it as an auxiliary controller or tiny customized microcontroller; inspect the license files for dependencies and generated deliverables. [NEORV32 project documentation] |
| Micro-riscy | PULP describes a minimal-area, 2-stage RV32-EC core with 16 registers and no hardware multiplier. | Considering a minimal-area design where its instruction-set limits fit the workload. | This is a project description, not a current common-condition comparison with the other cores. [PULP implementation page] |
What to know about each candidate
CV32E40P: a configurable core, not a full MCU
The OpenHW Group manual describes CV32E40P as “fully synthesizable.” It uses OBI instruction-fetch and load/store interfaces and is designed mainly for ASIC use, while FPGA synthesis is supported. The manual also notes that users must provide a clock-gating module for their target technology. Its documented instruction-set and extension options make the exact configured RTL important: optional features should not be mistaken for capabilities present in every build.
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The manual’s architecture description lists machine mode (M-mode) and says CV32E40P does not support RV32A atomics, user mode (U-mode), or a physical memory protection unit (PMP). That document is versioned v1.1.0, and its indexed content is older; verify the current RTL and documentation before relying on these details for a design. The manual traces the core’s history to RI5CY/PULP and records its contribution to OpenHW Group in February 2020.
CORE-V-MCU: a useful integration reference with defined limits
CORE-V-MCU shows how a processor becomes part of a larger embedded system. In addition to the CV32E40P v1.0.0 core, its overview specifies 512 KB of on-chip SRAM, an embedded FPGA resource, and the listed communication, I/O, timer, and debug peripherals. The overview names known physical configurations for an OpenHW GF-22FDX ASIC, a Digilent Nexys A7 with Artix-7, and a Digilent Genesys 2 with Kintex-7.
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Those configurations are evidence for the builds identified by the project, not proof that arbitrary peripheral combinations or a production deployment have been tested. Treat the overview as a bounded reference design: check that your intended configuration matches one of the documented combinations before planning around it.
Ibex and Micro-riscy: PULP’s control-oriented descriptions
PULP characterizes Ibex (called Zero-riscy in the page’s historical context) as an area-optimized, 2-stage, 32-bit core for control applications implementing RV32-IMC. It describes Micro-riscy as a smaller 2-stage RV32-EC option with 16 registers and no hardware multiplier. These descriptions help narrow candidates by design intent and ISA, but they do not establish current relative silicon area, power, or performance under shared test conditions.
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PULP also describes CV32E40P as a 4-stage core with optional FPU and DSP-oriented extensions, including hardware loops, SIMD, bit manipulation, and post-increment operations. Such extensions can matter for a workload, but they can also affect the implementation and software toolchain. Check the selected configuration and toolchain support rather than assuming every extension is enabled by default.
NEORV32: a configurable VHDL MCU-like route
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How to choose for a real IoT design
Use these criteria to evaluate the intended configuration, rather than ranking cores by a single “IoT-ready” label:
- Instruction set and software: Confirm the required base ISA and extensions, compiler support, and whether custom instructions would create a toolchain dependency.
- Core or system scope: Establish whether you are receiving CPU RTL alone or also memory, timers, serial interfaces, boot flow, debug, and software examples.
- Implementation target: Check HDL and tool-flow support, ASIC versus FPGA assumptions, timing-closure work, clock-gating requirements, and whether your exact configuration is documented as building.
- Area, power, and frequency: Compare only measurements made with the intended configuration, process or FPGA, voltage, clock, and workload. The cited project descriptions do not provide a current common-condition benchmark across these candidates.
- License and dependencies: Check the core, SoC, peripherals, libraries, and third-party IP individually. “Open source” at project level does not answer every reuse or distribution question.
- Verification and maintenance: Inspect current regression or compliance status, issue activity, documentation version, and release history. The cited project pages are not a complete audit of present-day maintenance.
- Product needs beyond the CPU: Plan separately for radio or network connectivity, security architecture, update path, safety requirements, memory capacity, manufacturing support, and lifecycle.
A practical evaluation sequence
- Write down workload and system requirements. Identify required ISA features, memory, peripherals, connectivity, debug, and target ASIC or FPGA before picking a candidate.
- Shortlist by scope. Investigate Ibex for a small control-oriented block; CV32E40P with CORE-V-MCU for optional DSP-style extensions and an OpenHW integration example; or NEORV32 when a VHDL MCU-like system and software framework are useful.
- Pin the design version and configuration. Record the RTL revision, enabled extensions and peripherals, toolchain, and target device or process. Do not assume a project’s default or listed example matches your product.
- Build and test that exact configuration. Use the project’s documented flow, then inspect current verification evidence and resolve integration issues before committing to the architecture.
- Review reuse terms and dependencies. Read applicable license files across the core, subsystem, and included components, including generated artifacts.
- Measure on the intended target. Establish area, power, and timing with the actual device or process, voltage, clock, and representative workload. Do not infer a general winner from figures produced under different conditions.
Recommendation
For a small control-oriented block, investigate Ibex and confirm that its ISA and integration requirements fit the application. For optional DSP-style extensions and a documented OpenHW route, evaluate CV32E40P alongside CORE-V-MCU. If a configurable VHDL system with software and debug infrastructure is the priority, consider NEORV32. These are architecture- and scope-based starting points, not measured winners: the choice should follow a build, license review, verification check, and target-specific measurement of the design you intend to ship.
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