“Multiple voltage dividers” can mean separate dividers sharing a supply, passive divider stages connected one after another, or one resistor ladder with several output taps. The key distinction is loading: separate branches do not normally change one another’s ratios on an ideal supply, but a downstream divider or other load changes the voltage of the stage feeding it. Calculate the connected network—not just the individual ratios—when outputs are not isolated.
What counts as multiple voltage dividers?
The phrase describes several different circuit arrangements. Identify which one you have before calculating it, because their outputs behave differently.
- Independent dividers: separate resistor pairs connected across the same supply and ground.
- Cascaded dividers: one divider’s output feeds another divider.
- Multi-tap ladder: several resistors in a series string, with outputs taken at different junctions.
- Loaded dividers: one or more outputs feed an ADC, amplifier, sensor, or other circuit.
A divider can also be part of a symmetrical network for differential or common-mode signals. In any topology, the output is measured relative to its stated reference node, usually ground.
Start with the basic divider and its source resistance
For an input voltage VIN, upper resistor R1 and lower resistor R2, the unloaded output at the junction is:
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VOUT = VIN × R2 / (R1 + R2)
The divider’s equivalent source resistance, also called its Thevenin resistance, is R1 ∥ R2, where ∥ denotes a parallel combination. The unloaded output is its Thevenin voltage. These two values provide a useful way to account for a load: treat the divider as a voltage source with a series resistance, then include the load. Analog Devices explains this source-resistance effect in its ADC source-resistance analysis.
If a load RL connects from the output to ground, it is in parallel with R2. Use R2,eff = R2 ∥ RL, then calculate:
VOUT = VIN × R2,eff / (R1 + R2,eff)
As the load resistance falls, the effective lower resistance falls and so does the output. This is why a real input cannot always be treated as an invisible voltmeter.
Independent dividers on one supply
When several divider branches connect to the same ideal voltage source and ground, each branch has its own ratio:
VOUT,i = VCC × R2,i / (R1,i + R2,i)
Each branch draws current from the supply. For branch i, Ii = VCC / (R1,i + R2,i); total divider current is the sum of branch currents. For example, two 10-kΩ/10-kΩ dividers across 5 V each draw 0.25 mA, for 0.50 mA combined. Their unloaded outputs are both 2.5 V.
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The branches do not directly load each other through an ideal source. A real supply has finite output impedance, however, so enough branch current can lower the voltage available to all of them. With source resistance RS, an approximate network voltage is VCC,actual = VSOURCE − RSITOTAL. Account for this if the source is a small battery, a GPIO pin, a long trace, or a regulator near its current limit.
Cascaded dividers: why ratios usually do not multiply
Multiplying stage ratios works only if the second stage does not significantly load the first. A buffer between stages can provide that isolation; otherwise, the second divider’s input resistance becomes a load on the first.
Consider this connection:
VIN ── R1 ──●── R2 ── GND
│
R3
│
●── VOUT
│
R4
│
GND
The second divider presents an input resistance of R3 + R4 from the first stage’s output to ground. That resistance is in parallel with R2. Calculate the first-stage output using that parallel combination, then apply the second stage’s ratio.
Worked example: four 10-kΩ resistors from 12 V
With R1 = R2 = R3 = R4 = 10 kΩ, multiplying two half-scale ratios suggests an output of 3 V. That assumes the first stage remains at 6 V when the second divider is connected.
- Find the second stage’s input resistance: R3 + R4 = 20 kΩ.
- Combine it with the first stage’s lower resistor: 10 kΩ ∥ 20 kΩ = 6.667 kΩ.
- Recalculate the first-stage output: VX = 12 V × 6.667 / (10 + 6.667) ≈ 4.8 V.
- Apply the second-stage ratio: VOUT = 4.8 V × 10 / 20 = 2.4 V.
The connected passive network produces 2.4 V, not the naïve 3 V. For more stages or branches, nodal analysis or a circuit simulator is often clearer than repeated hand reductions.
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Multi-tap resistor ladders
A resistor ladder uses one series string to create several tap voltages. For an unloaded string with resistors R1 through Rn, the same current flows through each resistor: I = VCC / (R1 + … + Rn). A tap voltage is the sum of the voltage drops below that tap. For example, with four resistors, the second tap down from the supply is VCC × (R3 + R4) / (R1 + R2 + R3 + R4).
Connecting a load to any tap changes current distribution and can shift other tap voltages too. Buffer taps that must remain stable under load, or calculate the complete loaded ladder rather than treating each section as an independent divider.
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A DC input-impedance specification is not always enough to decide whether a divider can drive an ADC. Many ADCs use a sampling switch and sample-and-hold capacitor; the input draws transient charge during acquisition. A high-resistance divider may appear correct on a multimeter but fail to settle to the required accuracy before conversion. Analog Devices discusses gain, settling and distortion effects from divider source resistance in its ADC analysis.
Check the ADC’s input model, acquisition time, sampling rate and recommended source resistance. TI’s C2000 ADC charge-sharing design example analyzes a 160-kΩ/1.2-kΩ divider with an equivalent resistance of about 1.191 kΩ and a 51-nF capacitor. Under that example’s settling assumptions, it calculates approximately 2.6-kHz filter bandwidth and a 23.5-kHz maximum sampling rate; these are example-specific figures, not universal limits.
A capacitor from a divider output to ground can filter noise and provide transient charge to an ADC. For an unloaded divider, the approximate corner frequency is fC = 1 / (2πRTHC), where RTH = R1 ∥ R2. With other loads connected, use the effective resistance seen by the capacitor. A capacitor also slows response to real voltage changes, lengthens startup settling and can introduce leakage error. For signals with substantial bandwidth or capacitive loading, a frequency-compensated attenuator may be needed; see Analog Devices’ frequency-compensated divider discussion.
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For amplifier inputs, check input resistance and bias current as well as offset and common-mode limits. A high nominal input resistance does not eliminate error from bias current flowing through the divider’s source resistance. Analog Devices’ AN-937 amplifier-design note describes how a divider used at an instrumentation-amplifier reference input can affect gain and common-mode rejection, and why buffering, filtering or a more suitable reference may be needed.
Choosing resistor values: current, settling and power
First choose the ratio required, then choose the total resistance based on current, loading, accuracy and speed. For an unloaded divider across VIN:
- Divider current: IDIV = VIN / (R1 + R2).
- Total resistor power: PTOTAL = VINIDIV = VIN2 / (R1 + R2).
- Individual resistor power: PR1 = IDIV2R1 and PR2 = IDIV2R2.
Higher values reduce continuous current but raise source resistance, RC settling time and sensitivity to input leakage, capacitor leakage, contamination and noise pickup. Lower values make the output stiffer and generally settle faster, but consume more current and dissipate more power. The right value depends on the load and error budget, not a universal resistor ratio. Analog Devices likewise treats divider resistance in power-supply feedback as application-dependent, balancing power loss, noise and circuit needs in its power-supply divider discussion.
For a target ratio k = VOUT/VIN, the unloaded relationship is R2/(R1 + R2) = k. Once a total resistance is selected, choose resistor values in that ratio, then recalculate with the actual load.
Accuracy, matching and error budget
Divider accuracy depends on the ratio of the resistors, not just their nominal values. Independent 1% resistors do not guarantee a 1% output ratio; for a near-half-scale divider, worst-case ratio error can approach about 2% before temperature, loading and source variation are included. Matching and tracking matter especially in paired networks: TI notes that divider mismatch can contribute to gain error, degraded common-mode rejection and temperature-dependent error in high-side current sensing in its common-mode range application note.
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Include the relevant contributors in the error budget:
- Resistor tolerance, temperature coefficient and voltage coefficient
- Supply variation and ground offsets
- ADC reference tolerance, input leakage and acquisition behavior
- Op-amp offset, bias current and noise, if buffered
- Protection-device and capacitor leakage
- PCB surface leakage, humidity and contamination
For precision scaling, consider 0.1% or better resistors, a matched network where ratio tracking matters, low-temperature-coefficient parts, and calibration if the required accuracy warrants it. A resistor network improves matching but does not remove errors from loading, reference variation or the ADC itself.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.When to buffer, regulate or use a dedicated IC
A unity-gain op-amp follower can isolate a divider from a following stage: the divider sees the amplifier input, while the amplifier output drives the load. It is useful when a divider feeds another divider, a variable load, a rapidly sampled ADC, or several circuits sharing a bias voltage. The amplifier must suit the supply voltage, input common-mode range, output swing, offset, bias current, noise, bandwidth and capacitive-load stability. A buffer adds its own errors and power consumption, so it is not automatically beneficial.
| Approach | Useful when | Main trade-off |
|---|---|---|
| Passive divider | Slow, high-impedance sensing with modest accuracy needs | Output voltage changes with load; current and settling depend on resistor values |
| Divider plus capacitor | Noise filtering or ADC charge support is needed | Reduced bandwidth and slower startup or response; leakage must be considered |
| Divider plus buffer | Isolation, lower output impedance or a changing load is required | Added amplifier cost, power and offset/noise/stability checks |
| Reference or regulator IC | A stable voltage must be maintained under load or supply variation | It is not a substitute for scaling a voltage that must be measured |
| Dedicated monitor or ADC IC | Many rails, fault thresholds or accurate telemetry are needed | May add cost and reduce flexibility compared with a few simple channels |
With multiple channels, options include one buffer per output for isolation, a multiplexer and shared buffer where channel-settling time permits, or a dedicated multichannel ADC or monitor IC. Select based on accuracy, sampling behavior, bandwidth, power, channel count and board area.
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High-voltage sensing and failure checks
When scaling a battery or other high voltage into an ADC, verify the maximum input, not just the nominal voltage. Check the ADC’s absolute voltage limits, input protection, supply sequencing and transient behavior. A divider does not level-shift a negative signal into a positive-only ADC range; negative or bipolar inputs need appropriate biasing, protection or a suitable input architecture.
At high voltages, check each resistor’s working-voltage rating as well as its power rating. A series string may be needed to share voltage stress and maintain appropriate spacing. Analyze maximum supply, tolerance, startup overshoot, fault voltage, temperature, creepage and clearance, as well as open- and short-resistor failure cases. Protection components can themselves add leakage and capacitance, so include them in the calculation.
Troubleshooting readings that do not match
- Output is lower than expected: Look for a downstream divider or load in parallel with the lower resistor, an overloaded source, or a supply that sags under total branch current.
- ADC readings are wrong but a multimeter looks right: Check source resistance, ADC acquisition time, sampling rate, input capacitance and channel-to-channel settling. A meter’s slow, high-impedance measurement does not reproduce ADC sampling.
- Reading is noisy or drifts: Check supply noise, ground offsets, high resistor values, input leakage, board contamination and capacitor leakage. A divider scales supply disturbance too; it is not inherently a precision reference. AN-937 discusses supply noise and transients reaching amplifier reference inputs.
- Voltage changes slowly after power-up: A large output capacitor and source resistance create a long time constant. Confirm that the filtering is worth the delayed response.
- Battery life is poor: Add the current of every divider branch and check whether the total resistance can be increased without violating leakage and settling requirements.
- One ladder tap shifts the others: Include that tap’s load in the complete ladder calculation or buffer the affected output.
A practical calculation and verification sequence
- Mark the topology and reference nodes. Identify independent branches, cascaded stages, ladder taps and every connected load.
- Calculate unloaded ratios and branch currents. Use the basic divider equation, then sum currents drawn from a shared source.
- Include downstream input resistance. Combine loads in parallel with the relevant lower resistor and recalculate upstream nodes.
- Check source resistance and settling. Compare the effective output resistance with ADC or amplifier requirements; include capacitor and acquisition behavior.
- Check errors and worst cases. Include resistor tolerances, temperature, source/reference variation, leakage, bias currents, protection parts and maximum input voltage.
- Choose isolation if needed. Decide whether a passive network suffices or whether a buffer, reference, regulator or monitor IC fits the requirement.
- Verify the circuit under actual conditions. Simulate complex networks or tolerance cases, then measure with the actual load across supply and operating conditions. For ADC work, verify conversion performance with the real ADC rather than relying only on a multimeter.
For larger networks, nodal analysis is less error-prone than assuming stage ratios multiply. SPICE tools such as LTspice or TINA-TI can help examine loading, RC response and tolerance cases, but the component and ADC specifications still govern the design.
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