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An LFSR updates a binary register by shifting its state and feeding back the XOR of selected bits. The tap positions define a recurrence; a primitive polynomial of degree n gives an XOR LFSR a maximum period of 2n − 1, excluding the all-zero state. This tutorial explains how to read that rule, compare common implementations, and check that a chosen polynomial and seed behave as intended.
What is a linear feedback shift register?
A linear feedback shift register (LFSR) is a finite-state machine whose state is held in a binary register. At each clock step, the bits shift by one position and a new bit is computed from selected bits in the current state. In the usual XOR implementation, the feedback bit is the XOR of the selected taps. Because XOR is addition over the two-element field GF(2), the feedback rule is linear.
An LFSR is deterministic: given the same initial state and update rule, it produces the same sequence. It is used to generate repeatable bit patterns in applications such as digital hardware tests, communications, and scramblers. Its output is not truly random. The University of Alberta ECE explanation describes the shift-register and combinational-feedback structure; IEEE Technology Navigator summarizes the polynomial relationship and applications.
How do feedback taps determine the next state?
A tap is a state bit included in the feedback calculation. For example, define a four-bit state as [b3,b2,b1,b0], shift toward the lower indices, discard the old b0, and insert b3 XOR b0 as the new b3. The recurrence is:
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[b3,b2,b1,b0] → [b3 XOR b0,b3,b2,b1]
Starting from 0001, the states begin 0001 → 1000 → 1100 → 1110 → 1111. This example demonstrates how to read a recurrence; it is not a claim that this tap choice has a maximal period. The displayed rule specifies the output convention, direction, indices, and feedback taps, so it can be implemented or checked without guessing what a diagram means.
The polynomial notation encodes the same recurrence, but conventions vary: authors may number bits from the opposite end, reverse the shift direction, define a different output bit, or include or omit the leading term. Thus, a polynomial alone is not enough to translate code reliably. State which bit is output, which way the register shifts, how taps are numbered, and whether the polynomial includes its leading term. The tap-to-polynomial relationship is described in the University of Alberta note and the IEEE overview.
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When does an LFSR reach its maximum period?
An n-stage XOR LFSR has at most 2n possible states, but its all-zero state is a fixed point: XORing zero-valued taps always produces zero, so the register cannot leave it. When the feedback polynomial is primitive and the seed is nonzero, the LFSR cycles through every nonzero state exactly once before repeating. Its period is therefore 2n − 1. An arbitrary polynomial or seed does not guarantee that period. The maximal-period condition is covered by IEEE Technology Navigator.
- Primitive polynomial: required for the maximal-length cycle under the specified XOR recurrence.
- Nonzero seed: required to enter that nonzero-state cycle; the zero seed remains locked at zero.
- Verified convention: the polynomial must correspond to the actual shift direction, bit indexing, and feedback rule in the implementation.
OpenTitan documents lockup handling for XOR and complementary XNOR implementations, along with its coefficient choices and verification approach, in its prim_lfsr documentation. Those implementation details are specific to OpenTitan, not general bounds on LFSR width.
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Fibonacci and Galois LFSRs: what changes?
Fibonacci and Galois describe different ways of organizing the feedback logic. Neither name, by itself, specifies the shift direction or bit numbering, so compare concrete recurrences rather than relying on labels alone.
| Form | Where feedback logic is applied | Practical consideration |
|---|---|---|
| Fibonacci | Selected taps are combined into a feedback value outside the register, then the value is shifted in. | The recurrence can be easy to read as one feedback equation; the combined logic path depends on the specific circuit. |
| Galois | Feedback is distributed through internal state updates at selected positions. | Internal state updates differ from the Fibonacci recurrence; verify the mapping, taps, and output convention for the particular implementation. |
Logic depth and timing depend on the actual circuit and target. A University of Alberta implementation discussion describes a shorter clock-to-clock path for a one-to-many implementation in its particular design context; that should not be treated as a universal advantage of a named LFSR form. For a hardware reference showing forms, seed handling, lockup protection, and checks, consult OpenTitan’s prim_lfsr documentation.
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How to choose and verify a feedback polynomial
Choose a polynomial only after deciding the register width and implementation convention. A listed polynomial is not evidence by itself that a specific code implementation has the desired period: reversing bit indices or shifting in the other direction can change the realized recurrence.
- Fix the state convention. Write down the register width, shift direction, output bit, tap numbering, and whether polynomial notation includes the leading term.
- Specify the recurrence. Identify the exact state bits that are XORed and where the resulting feedback bit enters. Use the same convention in the diagram, polynomial, and code.
- Use a verified primitive polynomial for a maximal period. Confirm that it is primitive for the recurrence convention in use; do not infer maximal length from polynomial degree alone.
- Select a nonzero seed. The all-zero state is locked under XOR feedback. Confirm any implementation-specific seed requirements as well.
- Check the transition function and period. Test successive states against the stated recurrence and, when a maximal period is required, verify the full cycle or use a suitable formal method. OpenTitan documents formal transition-function verification and a bounded simulation sweep for its own implementation.
OpenTitan reports that its documented coefficient set ranges from 3-bit to 168-bit, and that polynomials up to 34 bits were swept in simulation for maximal length. These are facts about that project’s implementation and verification, not universal LFSR limits or a guarantee for a different design. See the OpenTitan documentation.
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Can an LFSR be used for cryptography?
A long period does not make an LFSR cryptographically secure. The recurrence is linear, and linear complexity is the length of the shortest LFSR capable of reproducing a sequence. The Berlekamp–Massey algorithm can reconstruct a shortest linear recurrence from sequence data. An IEEE paper on sequence complexity states that LFSRs cannot ensure large linear complexity unless their lengths are prohibitively high: “On the linear complexity of nonlinearly filtered PN-sequences”, published November 30, 2003.
Use a plain LFSR for deterministic sequence generation where its properties are appropriate, not as a secure keystream generator. A cryptographic system requires a separately justified construction; an LFSR’s period alone does not supply that security.
Implementing an LFSR in hardware
An FPGA is one way to implement and observe LFSR logic, but no particular board is required to understand or simulate the recurrence. AMD’s XAPP210 application note discusses LFSRs in Virtex devices; its implementation advice is tied to that device context and should not automatically be applied to every FPGA generation. OpenTitan’s primitive documentation provides another hardware implementation reference.
For a first implementation, make the recurrence the source of truth: write the state update, simulate from a known nonzero seed, and compare each next state with hand-calculated steps. If the simulation disagrees, check bit order, shift direction, whether the old or updated state is used in feedback, and whether the polynomial convention matches the code.
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