Choose a clock-domain crossing (CDC) method based on what crosses the boundary: use a destination-clock synchronizer for a single-bit level, a pulse-safe protocol for an event, a request/acknowledge handshake for occasional transfers, and a dual-clock FIFO for coherent multi-bit data or bursts. Then budget the added latency, define reset and backpressure behavior, and verify the crossings before hardware sign-off.
First classify every crossing
A design with multiple clocks needs an explicit map of which signals move between them. For each crossing, identify the source and destination clocks, reset domains, signal ownership, transfer rate, and whether the receiver can tolerate delay, a dropped event, or backpressure. Classify the crossing as one of three cases:
- Single-bit control: a level or event such as a status flag or request.
- Coherent multi-bit data: a word or bus whose bits must be received as one valid value.
- Bus transaction: a command, response, or stream with transaction ordering and completion semantics.
AMD’s Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387, 2026.1) states that CDC circuits directly affect design reliability. That is why a crossing should be treated as part of the architecture, not as incidental wiring.
Which CDC strategy fits?
| Crossing | Usual strategy | Best fit | Main design concern |
|---|---|---|---|
| Single-bit level | Registered synchronizer chain in the destination clock domain | A control level that remains asserted long enough to be sampled | Keep the synchronized result in the destination domain; do not assume a short pulse will be observed. |
| Single-bit event or pulse | Pulse stretching, a toggle protocol, or request/acknowledge | An event that must not be missed when clocks are unrelated | Provide a protocol that holds or encodes the event until the destination can observe it. |
| Low-rate command or response | Request/acknowledge handshake | Occasional transfers where resource use matters more than peak throughput | The next transfer must wait until the current transfer has safely propagated and completed. |
| Multi-bit data, bursts, or streaming | Dual-clock FIFO or buffered clock-crossing bridge | Repeated transfers or data that must remain coherent across clock domains | Handle full and empty status, buffering, and backpressure using signals valid in the appropriate clock domain. |
Single-bit controls and events
Pass a stable single-bit level through a registered synchronizer in the receiving domain. A brief source-domain pulse can fall entirely between destination clock edges, so use pulse stretching, a toggle, or a request/acknowledge exchange when the event must be delivered reliably. Choose the protocol according to whether the source can wait and whether another event can arrive before the first is handled.
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Low-rate transfers
A request/acknowledge handshake is suited to commands and responses that do not need to arrive every cycle. Intel’s Platform Designer User Guide describes its Handshake adapter as appropriate for low-throughput requirements: one transfer is safely propagated before the next begins. This simplicity comes with transaction time spent waiting for the exchange to complete.
Bursts and streams
For repeated multi-bit transfers, use a dual-clock FIFO or a buffered clock-crossing bridge rather than synchronizing each data bit independently. The FIFO carries data with controlled availability and full/empty behavior; AMD’s UltraScale Architecture Configurable Logic Block User Guide (UG574) describes a dual-clock FIFO as a way to pass data between differing clock domains while avoiding ambiguity, glitches, or metastability problems. Intel notes that FIFO adapters support multiple transactions and higher throughput than handshake adapters, at greater resource cost.
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How much latency should you budget?
There is no single CDC latency figure for every design. It depends on the selected structure, clock rates and phase relationship, adapter configuration, buffering, and whether the transfer blocks while waiting for capacity or acknowledgement. Treat the figures below as specific to the cited Intel configurations rather than as universal CDC costs.
| Documented figure | Scope and qualification |
|---|---|
| Approximately two additional clock cycles | Intel/Altera documentation dated 2025-12-15 reports FIFO-adapter latency as approximately two cycles more than the handshake component. |
| Up to five host and five agent clock cycles | Intel’s 2023 documentation gives this worst-case read overhead for its stated default configuration; the counts are in the host and agent clock domains. |
| Up to four times throughput after initial pipeline fill | Intel’s 2023 documentation gives this potential throughput increase for a pipelined clock-crossing bridge, with added logic-resource cost. |
For an end-to-end deadline, account for crossing latency along with queueing, backpressure, and any blocked transaction time. A design that can accept bursts but pauses when a FIFO fills needs a deadline analysis that includes that pause, not just the nominal transfer rate.
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How should SPI and I²C use interrupts, FIFOs, or DMA?
SPI: keep up with the master’s clock
Xilinx documents SPI as a four-wire, full-duplex synchronous bus in which the master controls the clock. A slave therefore needs transmit data ready at the master’s pace while also receiving data. For higher-rate transfers, matched transmit and receive FIFOs can buffer both directions; DMA or interrupt thresholds can reduce how often software must service the peripheral. The Xilinx driver warns that without FIFOs, interrupt frequency follows the data rate, so CPU service pressure rises as transfers speed up.
I²C: decouple byte timing from software service
Silicon Labs’ controller documentation lists programmable timing, FIFO buffering, interrupt-driven and DMA-based operation, clock synchronization, and bus-clear features. These capabilities can help when multiple devices share a bus or software cannot service every byte at the instant it arrives. The same documentation, version 1.0.2, specifies high-performance I²C modes up to 3.4 Mbps for its documented controller family; that figure should not be generalized to all I²C controllers or devices.
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Implementation and review checklist
- Map domains: draw every clock and reset domain, and mark who owns each signal.
- Classify each crossing: distinguish single-bit control, coherent multi-bit data, and bus transactions.
- Select the transfer structure: use a synchronizer, pulse-safe or request/acknowledge protocol, or dual-clock FIFO as appropriate.
- Keep status local: do not consume full, empty, acknowledgement, or other status directly from an unrelated clock domain; use status valid in the receiving domain.
- Constrain and identify CDC logic: apply the vendor-recognized constraints, attributes, or primitives. AMD notes that XPMs and correct
ASYNC_REGapplication support implementation and reliability. - Budget the complete path: include synchronizer or FIFO latency, blocking behavior, buffering limits, and backpressure in deadline calculations.
- Define peripheral policy: specify SPI and I²C FIFO thresholds, interrupt coalescing, DMA ownership, timeout behavior, bus recovery, and reset sequencing.
- Verify failure boundaries: use static CDC analysis and hardware timing or protocol capture; test reset release, clock stoppage, burst overflow and underflow, and metastability-sensitive boundaries.
How to choose when more than one option works
Compare viable approaches against the actual workload rather than choosing only for nominal throughput. The decision should account for:
Quick Recap
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- Data rate and burstiness, including whether transfers arrive continuously or in occasional commands.
- Allowed latency and jitter, especially for deadline-sensitive responses.
- Required buffering depth and what happens when that capacity is exhausted.
- Logic-resource and power cost.
- Backpressure semantics and whether the source can pause.
- Reset behavior and how each side knows a transfer can resume safely.
- Verification complexity and whether dropped, repeated, or reordered events are acceptable.
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