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Implementing I²C on an STM8S in IAR Embedded Workbench is reliable when you treat it as three separate jobs: verify the exact MCU pins and electrical bus, calculate timing from the actual peripheral clock, and follow the STM8S event-clearing and ACK sequences in RM0016. IAR builds and debugs the firmware; it does not fix pull-ups, addresses, timing registers, or bus faults.
Scope and prerequisites
This guide targets STM8S devices that actually include the I²C peripheral, such as selected STM8S003/103/105 variants. Confirm the complete part number, package, datasheet pinout, alternate-function settings, and errata before copying code. ST’s family documentation is available from STM8S series documentation and STM8S103/105 documentation.
- Use a known peripheral input clock, not an assumed CPU frequency.
- Assume a 7-bit slave address and external pull-ups unless your hardware documentation says otherwise.
- Choose Standard mode (nominally 100 kHz) or Fast mode only after checking the exact device datasheet, rise time, voltage and bus capacitance.
- Use timeouts in every polling loop.
Hardware: pins, pull-ups and voltage
Find SDA and SCL in the exact device datasheet. Family names do not guarantee identical pin mappings, and small packages may not expose every alternate-function pin. Configure those pins for the I²C-capable open-drain function required by that device; do not leave them as ordinary push-pull GPIO.
I²C lines are released high and require pull-up resistors. Check that both lines rise to the bus voltage, that all devices share ground, and that the voltage is within the STM8S and peripheral limits. Resistor selection depends on voltage, bus capacitance, speed and sink-current limits, so no single value is universal. A logic analyzer must use a threshold suitable for the actual voltage.
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What IAR does—and does not do
IAR Embedded Workbench supplies the STM8 compiler, linker, assembler, debugger and project environment; STM8 is listed as a supported architecture on IAR’s STM8 page and the Embedded Workbench product page. It does not configure board pull-ups, discover a slave address, select the correct pins, or replace the STM8 reference manual.
The public update page currently lists EWSTM8 3.11.4, published June 21, 2021: EWSTM8 updates. Verify the installed release before relying on menu labels or debugger behavior; do not assume STM8 receives updates on the same cadence as newer IAR toolchains.
Create and configure an EWSTM8 project
- Install EWSTM8 and select New Project for an STM8 C project.
- Select the exact target device, not a generic STM8 family.
- Add the application and I²C driver sources, then include the matching device header.
- Select the linker configuration that matches the device’s flash and RAM size.
- Set compiler optimization and runtime-library options appropriate to the product.
- Build and inspect the map file for code and RAM usage.
- Connect a supported debug probe and target board, then program and debug. IAR’s STM8/ST-LINK workflow is documented in this getting-started guide.
The IAR development guide is at EWSTM8 Development Guide; IDE details are in the EWSTM8 IDE Guide.
STM8S I²C peripheral model
The peripheral can operate as master or slave. In master mode, firmware generates START, sends an address and direction bit, transfers bytes MSB-first, handles ACK/NACK, and issues STOP. The principal registers are I2C_CR1, I2C_CR2, I2C_FREQR, I2C_DR, I2C_SR1, I2C_SR2, I2C_SR3, I2C_CCRL, I2C_CCRH and I2C_TRISER. The authoritative sequencing is in ST RM0016.
Calculate timing registers
Peripheral clock and FREQR
I2C_FREQR contains the I²C peripheral input clock in MHz. RM0016 specifies at least 1 MHz for Standard mode and 4 MHz for Fast mode. These are peripheral-clock requirements, not the desired SCL frequency. If the clock tree divides or switches the peripheral clock, use that actual value.
Standard mode
For Standard mode:
fSCL = fMASTER / (2 × CCR)CCR = fMASTER / (2 × fSCL)
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At 16 MHz and a nominal 100 kHz bus, CCR = 80 (0x50). At 8 MHz, CCR = 40 (0x28). RM0016 gives the 8 MHz example and specifies a minimum Standard-mode CCR of 0x04.
Fast mode
With DUTY = 0, fSCL = fMASTER / (3 × CCR); with DUTY = 1, fSCL = fMASTER / (25 × CCR). RM0016 describes the corresponding low/high ratios as 2:1 and 16:9. Check electrical limits and measured rise time before claiming 400 kHz operation.
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Use TRISE = maximum_allowed_rise_time / tMASTER + 1. At 8 MHz, tMASTER = 125 ns; using the 1000 ns Standard-mode maximum gives TRISE = 9 (0x09). At 16 MHz the same assumption gives 17. Program TRISE while PE = 0; these values are not universal constants.
Initialization order
- Configure the MCU clock and determine the I²C peripheral clock.
- Configure the selected SDA/SCL alternate-function GPIO mode.
- Verify pull-ups and voltage compatibility.
- Disable I²C while changing timing registers.
- Write
I2C_FREQR,I2C_CCRL/I2C_CCRHandI2C_TRISER. - Set ACK and interrupt policy.
- Enable the peripheral with
I2C_CR1.PE. - Confirm the bus is idle before START.
/* Register-level template; replace symbols with the selected device header. */
I2C_CR1 = 0x00; /* PE = 0 while timing is programmed */
I2C_FREQR = 16; /* actual peripheral clock, MHz */
I2C_CCRH = 0x00; /* Standard mode, DUTY = 0 */
I2C_CCRL = 80; /* 16 MHz, nominal 100 kHz */
I2C_TRISER = 17; /* 16 MHz and 1000 ns rise-time assumption */
I2C_CR2 = 0x00; /* no START or STOP yet */
I2C_CR1 = 0x01; /* PE = 1 */This is a template, not a universal driver. Confirm reset values, header symbols, pin mapping and errata for the selected part.
Addressing and a blocking master write
Keep the API unambiguous by accepting a 7-bit address:
uint8_t address_byte = (address7 << 1) | read_bit;For example, a 7-bit address of 0x50 becomes wire byte 0xA0 for write and 0xA1 for read. Do not pass 0xA0 to a function that shifts its argument again.
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- Wait for
I2C_SR3.BUSYto clear, with a timeout. - Set
I2C_CR2.STARTand wait forI2C_SR1.SB. - Read
SR1, then write the 8-bit address byte toI2C_DRto clear the START event. - Wait for address acknowledgment and clear ADDR using RM0016’s required status-register read sequence.
- For each byte, wait for TXE or the applicable transfer event, write
I2C_DR, and check AF, BERR, ARLO and timeout. - After the final transfer condition (typically TXE/BTF), set STOP and wait for BUSY to clear.
Never wait forever. Return a status such as OK, NACK, bus error, arbitration lost or timeout.
Master reads: ACK timing matters
One byte
- Generate START and send the address with the read bit.
- Disable ACK at the required point.
- Clear ADDR using the prescribed sequence.
- Set STOP immediately at the required point.
- Wait for RXNE, read
I2C_DR, and verify the bus returns idle.
RM0016 warns that this sequence must complete before the current byte’s ACK pulse.
Multiple bytes
- With more than two bytes remaining, continue ACKing received bytes.
- With two bytes remaining, use the STM8S-specific POS/ACK sequence from RM0016.
- For the final byte, disable ACK, clear ADDR at the required point, issue STOP, then read the byte.
A generic “read until RXNE” loop loses the final-byte timing and commonly produces a missing or extra byte.
Combined write/read transactions
Sensor-register and EEPROM accesses normally use one bus ownership sequence:
START
slave address + write
register or memory address
REPEATED START
slave address + read
data bytes
NACK
STOPImplement this as one combined-transfer operation. A repeated START is not equivalent to STOP followed by a new START; retaining ownership can be required by the peripheral being addressed.
Polling or interrupt-driven code?
| Approach | Best fit | Trade-offs |
|---|---|---|
| Polling | Bring-up, boot-time access and short, infrequent transfers | Simple and traceable, but blocks the CPU and requires timeouts |
| Interrupt state machine | Longer transfers, tight real-time work or concurrent activities | Non-blocking, but more complex ACK/error sequencing |
For interrupts, enable the appropriate buffer, event and error sources through I2C_ITR and use explicit states such as IDLE, START_SENT, ADDRESS_SENT, TRANSMIT_DATA, REPEATED_START, RECEIVE_DATA, SEND_STOP, COMPLETE, ERROR and RECOVERY. Keep blocking loops out of the ISR.
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Debug with a logic analyzer
Check the electrical bus before stepping through C: correct pins, common ground, pull-ups, voltage, and no device holding SDA or SCL low. A valid trace should show START, a 7-bit address plus R/W bit, ACK or NACK, data bytes with ACK/NACK, and STOP.
| Flag | Diagnostic meaning |
|---|---|
SB |
START completed; write the address to DR |
ADDR |
Address phase completed; clear with the prescribed reads |
TXE |
Transmit register empty |
RXNE |
Received byte available |
BTF |
Byte transfer finished; timing matters before STOP or the next byte |
AF |
NACK, often wrong address, direction, absent device or intentional slave NACK |
BERR |
Illegal START/STOP or electrical disturbance |
ARLO |
Arbitration lost |
OVR |
Overrun or underrun |
BUSY |
Bus occupied or physically stuck |
Record SR1, SR2, SR3, CR1, CR2, FREQR, CCRL, CCRH and TRISER when an operation fails. Compare the first failing flag with the waveform to separate GPIO, address, event-clearing, direction and STOP problems.
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Immediate AF
Verify 7-bit versus shifted address, the R/W bit, address-select pins, device power/reset state and wiring. A public API that accepts only address7 prevents double shifting.
BUSY stuck or lines low
Inspect SDA and SCL physically. A slave may be stretching SCL, or a reset may have left it expecting clocks. On timeout, disable I²C, preserve status registers, recheck line levels, optionally pulse SCL as GPIO if the hardware permits, issue a recovery STOP-like sequence, reinitialize and report an error.
Wrong frequency or intermittent NACKs
Recalculate FREQR from the actual peripheral clock, CCR from the selected mode and target rate, and TRISE from rise time. Measure SCL rather than trusting constants copied from another clock configuration.
Stalled transfer or missing first byte
Check that START and ADDR are cleared exactly as RM0016 specifies. Reading the wrong status registers, or reading them in the wrong order, can leave SCL held low or discard the first data byte.
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Works at 100 kHz but not Fast mode
Measure edge rise time, verify pull-up strength and capacitance, and confirm the exact MCU datasheet permits the selected conditions. Fast-mode formulas and peripheral support do not override electrical limits.
Register driver, library or bit-banging?
Direct registers
Register code exposes the STM8S flag-clearing order and avoids dependence on legacy library assumptions, but it is verbose and header-specific.
ST peripheral library or examples
Libraries can speed initial development, yet packages may target another device or compiler and may hide mandatory event sequences. ST’s software documentation, including material such as AN2737, is indexed at STM8 embedded-software documentation. Verify every function’s address convention and exact part support.
Bit-banged GPIO
Software I²C can be a fallback when pins or peripheral behavior make hardware I²C unsuitable, but it consumes CPU time and must still implement open-drain signaling, clock stretching, arbitration policy and recovery. Hardware I²C is normally preferable when the peripheral and pins are available.
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IAR is a sensible choice when an existing STM8 project, compiler ABI, debugger workflow or organizational standard requires it. IAR offers a free evaluation described at its free-trials page; the page states that evaluations last 14 days and include non-commercial-use restrictions and other limitations. For a new, cost-sensitive project, verify current pricing, support terms, device coverage and probe compatibility before committing.
Frequently Asked Questions
Should an STM8S I²C function accept a 7-bit or 8-bit address?
Prefer a 7-bit address in the public API and shift it internally, adding the read/write bit exactly once.
Are CCR and TRISE values portable between STM8S projects?
No. They depend on the actual peripheral clock, bus mode, target SCL rate, duty cycle and rise time.
Why does the bus hang after the address phase?
Common causes are incorrect ADDR-clearing reads, a missing ACK, a slave stretching SCL, or a physically held-low line.
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