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1Clear out junk files and repair common Windows errors2Fix the driver behind crashes, sound loss and screen glitches3Repair Windows errors before they cause bigger problemsLauterbach announced on June 3, 2025, that TRACE32 supports PX5 RTOS with OS-awareness. In practical terms, the integration is intended to let engineers inspect PX5 operating-system objects such as threads and message queues, view the software stack from application code through drivers, and analyze selected behavior over time in TRACE32 PowerView. The announcement describes capabilities, but not a universal hardware configuration or setup procedure.
What PX5 OS-awareness adds to TRACE32
OS-awareness brings operating-system structures and objects into the debugging workflow, rather than limiting inspection to application code and processor state. Lauterbach says its PX5 support exposes internal structures and data so developers can examine application behavior and chip-resource use.
The announced object-level examples are threads and message queues. The stated software view runs from the application through the operating system to device-driver code. This can help an engineer relate what an application is doing to the OS objects and lower-level software involved; the announcement does not specify a complete list of inspectable PX5 objects.
What engineers can inspect and analyze
Current OS-object state
TRACE32 PowerView is described as offering a static view of current PX5 OS-object state. This is the point-in-time side of the workflow: inspect relevant objects and their state while investigating a live debugging session.
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Behavior over time
The release also describes dynamic analysis of OS objects over time, naming task-scheduling analysis, symbolic function-call trace, and performance analysis. These are capabilities listed by Lauterbach; the announcement does not quantify their runtime overhead, trace requirements, or performance impact for a particular target.
What the announcement does—and does not—establish
The June 3, 2025 announcement establishes that Lauterbach says TRACE32 now supports PX5 RTOS with OS-awareness. It does not give a target-specific recipe for enabling that support. It does not identify supported processor families or boards, minimum TRACE32 or PX5 versions, required debugger hardware or trace interface, licensing terms, or a setup sequence.
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Before planning an implementation, confirm those details against current PX5-specific Lauterbach documentation or with Lauterbach support. In particular, verify compatibility for the actual processor and board, the required software versions, what hardware is needed for the analyses you intend to use, and whether any licensing or support arrangement applies. Lauterbach’s OS-awareness overview provides general product context, but it is not a substitute for PX5- and target-specific requirements.
PX5 figures and certifications are vendor claims
The announcement also includes PX5 performance, footprint, coverage, and certification statements. These are PX5/Lauterbach vendor-reported claims, not independent measurements of the TRACE32 integration. The release says PX5 provides sub-microsecond context switching and API calls on most microprocessors, and has a memory footprint of less than 1 KB. It also claims 100% statement and branch-decision coverage, describing extensive testing without supplying an independent test report in the cited material.
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The certifications named in the announcement are IEC 61508 SIL 4, IEC 62304 Class C, ISO 26262 ASIL D, and EN 50128 SW-SIL 4. The announcement alone does not establish the scope of a certificate or how it applies to a particular product configuration or use case; obtain current primary certification materials before relying on those claims for a project decision.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to evaluate the integration for a project
Use the announcement as evidence of the stated debugging capabilities, then validate fit against the intended target and workflow. A useful technical evaluation should establish:
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- Whether the processor or board and its trace interface are supported for the required debugging tasks.
- Which TRACE32 and PX5 software versions are compatible.
- Which OS objects can be inspected, including the specific thread, queue, or other structures needed by the team.
- Whether the needed analysis is point-in-time inspection, time-based scheduling analysis, symbolic function-call trace, performance analysis, or some combination.
- What hardware, licensing, and support arrangements are required, and what overhead the selected analysis introduces on the target.
Those are implementation questions to resolve with current target-specific documentation and vendor support; the announcement does not answer them. It likewise does not provide an independent comparative evaluation against other debugging products.
Quick Recap
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