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Do not treat AI-generated RTL as correct just because it parses or simulates. Verify it against an independently written behavioral contract, then check it with the tools and settings intended for your design flow. Parsing, lint, simulation, formal verification, and synthesis acceptance each answer different questions; none can compensate for a missing or incorrect specification.
What “verified before synthesis” should mean
Before synthesis, you want evidence that the RTL matches the required behavior and that the exact downstream synthesis frontend accepts the source under the intended configuration. This is a practical engineering workflow, not a universal sequence mandated by a standard. Adapt it to the design, HDL dialect, toolchain, and project sign-off rules.
Keep the specification as the reference point. A simulator checks the scenarios your tests exercise; a formal tool checks properties under its model and assumptions; a synthesis frontend checks what it can accept and interpret. None can establish that an incomplete or mistaken specification captures the design’s real requirements.
Follow a pre-synthesis verification workflow
1. Write down the behavioral contract
Document what the block must do before reviewing the generated implementation. Include the interface protocol, reset behavior, clocks, parameter ranges, observable outputs, boundary cases, and defined error behavior. Where practical, derive a small reference model or independent expected-value checks from the specification.
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2. Review the generated RTL against that contract
Check module names and ports, widths and signedness, reset polarity and priority, state transitions, and blocking versus nonblocking assignments. Inspect default assignments and case behavior, and look for unintended latches, multiple drivers, uninitialized state, accidental truncation or extension, and constructs that may be unsupported by the target synthesis flow.
These are practical review targets, not an AI-specific error-rate claim or a universal checklist. A code review can identify suspicious implementation choices, but behavioral checks are still needed.
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3. Parse and elaborate with explicit flow settings
Use the HDL mode, include paths, defines, parameter values, and top-level selection intended for the design flow. Classify and resolve warnings rather than suppressing them wholesale. A successful parse or elaboration means only that the selected frontend accepted the source under those settings; it does not show that the behavior matches intent.
4. Run lint and track every warning
Lint can surface suspicious widths, unused or undriven signals, incomplete assignments, implicit nets, unreachable branches, and coding patterns that may imply unintended hardware. For each warning, record whether it was fixed, intentionally waived, or remains open, and why. Select rules appropriate to the project and toolchain; no single lint rule set is established for every design.
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5. Simulate tests derived from the specification
Build the testbench from the behavioral contract, not from assumptions inferred from the generated code. Exercise reset and startup, normal transactions, boundary values, back-to-back events, defined protocol violations, and relevant state sequences. Check outputs and timing expectations with assertions or a reference model. Randomized tests can broaden scenario coverage; record seeds and failures so a result can be reproduced.
IEEE 1800-2023 describes SystemVerilog support for testbenches using coverage, assertions, object-oriented programming, and constrained-random verification. Those capabilities do not prescribe a test count or coverage threshold: passing simulation means the tested scenarios passed, not that all possible behavior is correct. The IEEE Standards Association lists the standard’s publication date as 28 February 2024 on its IEEE 1800-2023 page.
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6. Specify formal properties where they add value
Formal verification can examine properties such as legal state transitions, handshake stability, bounded response, mutual exclusion, counter limits, or data ordering. Make clocks, reset behavior, and environmental assumptions explicit. A formal tool reasons about the model and constraints supplied; assumptions that are too restrictive can hide reachable failures.
Inspect counterexamples and proof status, and check that properties are neither vacuous nor weaker than the requirements. YosysHQ’s SymbiYosys documentation describes its formal verification flow, while its formal extensions to Verilog documentation covers formal inputs and assumptions. A proof establishes the stated property under the modeled assumptions; it does not establish that every requirement was captured.
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7. Check acceptance with the actual synthesis frontend
Run the synthesis frontend and configuration intended for the project, using the relevant source set and parameter values. Review unsupported-construct diagnostics and inferred hardware. A simulator or formal frontend accepting a construct does not establish that the synthesis frontend accepts it or interprets it identically.
Language support varies by tool. Yosys’s README describes an informally defined synthesizable SystemVerilog subset; Verilator’s Input Languages documentation lists support by language feature. Check the documentation for the versions and settings actually used in your flow.
8. Keep verification evidence with the RTL revision
Retain the RTL and specification revisions, tool versions and options, testbench and random seeds, lint results and waivers, formal properties and assumptions, proof or counterexample logs, and synthesis diagnostics. This makes the basis for accepting the candidate implementation reviewable and helps reproduce failures later.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What each check can and cannot tell you
| Check | Evidence it provides | Important limit |
|---|---|---|
| Parse and elaborate | Diagnostics about syntax, hierarchy, parameters, and constructs visible to the selected frontend under its settings. | Does not demonstrate that behavior matches the specification or that another frontend will accept the RTL. |
| Lint | Warnings about suspicious coding patterns, widths, assignments, and signal use. | Does not prove functional correctness; warnings need project-specific review. |
| Simulation | Results for the scenarios and checks exercised by the testbench. | Does not cover behavior the tests do not exercise. |
| Formal verification | Proof status or counterexamples for stated properties under the supplied model and assumptions. | Does not validate omitted requirements; results depend on assumptions and tool support for the design’s constructs. |
| Target synthesis frontend | Acceptance diagnostics and information about the hardware inferred by the intended flow. | Acceptance alone does not prove the implementation satisfies its behavioral requirements. |
Compare checks by the question each answers, the model and scope used, the evidence produced, coverage limits, and compatibility with the project’s HDL version and downstream frontend. These checks are complementary rather than interchangeable.
Standards and project-specific sign-off
IEEE Std 1800-2023 covers hardware modeling at behavioral, RTL, and gate-level abstractions, as well as testbench techniques including coverage and assertions. IEEE 1012-2024 is a verification and validation process standard; its record is available from IEEE Xplore. Standards and tool documentation provide capabilities and process context, but they do not supply one official end-to-end checklist specific to AI-generated RTL. Your project must define its toolchain, applicable language features, requirements, and acceptance criteria.
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