Processor redundancy improves reliability by giving critical work another processing path, then detecting a fault and either transferring control or putting the system into a defined safe state. It is not a guarantee: the processors, power, communications, software, and fault-detection logic must be independent enough to withstand the failures the design targets, and the failover must be tested under operating conditions.
What processor redundancy does—and what it cannot guarantee
A redundant design adds processing capacity so one processor failure does not automatically become a system failure. Depending on the application, a second unit may take over, multiple units may compare results, or the system may shut down or move to a safe state when it detects disagreement.
The U.S. rail-safety criteria in 49 CFR Appendix C define checked redundancy as two or more identical, independent hardware units executing identical software and functions, with their operation checked. If the units disagree, safety-critical outputs must be driven to a known safe state. This is a safety architecture, not simply a count of processors: it depends on effective comparison, fault response, and a defensible definition of independence.
Redundancy also does not establish a universal reliability improvement or make every fault survivable. A design can retain a single point of failure in a shared power supply, clock, communication link, sensor, actuator, software defect, or environmental exposure. The useful question is whether the architecture tolerates the particular failures and operator errors identified for the system.
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Which processor redundancy architecture fits the job?
Choose according to what must happen when a processor fails or produces a wrong result. The relevant trade-offs include fault tolerance, fault-detection coverage, exposure to common causes, switchover behavior, cost, power, engineering complexity, and maintainability. No cited standard or guidance establishes one architecture as best for every application.
| Architecture | How it responds | Best suited to | Key limitation or design question |
|---|---|---|---|
| Dual active/standby (hot standby) | One processor controls the process; a synchronized partner is ready to assume control if the active unit fails. | Systems that need continuity and can transfer control to a prepared partner. | Establish synchronization integrity, independent power and communication paths, and actual switchover behavior. A standby CPU does not by itself prove that the whole control path is redundant. |
| Checked dual redundancy or lockstep | Two units perform the same function and a checker compares vital parameters or outputs. A disagreement triggers the specified response, such as a safe state. | Safety-critical systems where detecting an incorrect result and responding deterministically matters more than uninterrupted operation. | Two units can share the same design fault or external cause. Define what is compared, how quickly disagreement is detected, and what safe state follows. |
| Diverse or N-version programming | Independently developed software implementations run concurrently and their results are compared. | Cases where reducing the chance of a shared software design fault justifies additional development and verification work. | Independent development does not eliminate common requirements errors, integration faults, or shared hardware and input failures; the extra implementations also require verification and maintenance. |
| Triple modular redundancy (TMR) or majority voting | Three channels produce results that are voted; a faulty channel can be outvoted and isolated under the design’s fault assumptions. | Applications that must continue despite a fault in one channel and can support voting and channel isolation. | Voting logic and shared dependencies can themselves fail. The sources cited here do not establish a universal product recommendation or prove that TMR is preferable for a particular system. |
When uninterrupted handover matters
Siemens documents a specific hot-standby example in its S7-400H fault-tolerant process-control system: a backup CPU is event-synchronized with the master and performs the same processing. The manual says that if the active CPU fails, the standby continues the user program without delay, and describes the failover as bumpless for the ongoing process. That claim applies to the documented S7-400H configuration, not to every dual-CPU system. For any product, verify the supported configuration and measure the transition in the actual application.
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- This PM861AK02 3BSE018160R1 redundant processor unit module features a 32-bit reduced instruction set computing core with 2MB of on-board non-volatile memory for reliable industrial control operations.
- The module is designed to integrate with standard industrial automation control bus architectures, supporting 24V DC input power and compatible with common industrial fieldbus communication protocols.
- Constructed with flame-resistant, heat-conductive industrial-grade plastic and metal housing, the unit operates reliably in temperature ranges of 0 to 60 degrees Celsius and humidity levels up to 95% non-condensing.
- Ideal for use in factory automation assembly lines, material handling systems, and process control environments where continuous, uninterrupted programmable logic controller operation is required.
- The redundant processor design includes automatic failover functionality to minimize downtime, with status indicator LEDs for quick monitoring of operational health and communication status.
When a safe response matters more than staying online
Checked redundancy is not simply hot standby with a different name. Its central function is to compare independent results and react to disagreement. In the rail-safety criteria, that response is to put safety-critical outputs into a known safe state. If a process cannot safely continue with uncertain computation, an intentional safe shutdown may be more appropriate than attempting a fast transfer.
How to make redundant processors genuinely independent
Independence is a reliability property to demonstrate, not an assumption based on separate CPU modules. NASA NPR 8715.3 requires redundancy to tolerate the specified number of failures or operator errors and calls for common-cause failures—such as contamination or close proximity—to be addressed. It also requires safety-critical redundancy to be verified under operational conditions.
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- 【HIGH-PERFORMANCE H7 PROCESSOR】 Equipped with a powerful 32-bit STM32H743 ARM Cortex-M7 core running up to 480MHz, featuring 2MB Flash memory and 1MB RAM. Delivers the massive computing power required for complex autonomous vehicle algorithms, ensuring efficient and productive development work.
- 【DUAL REDUNDANT IMU & TEMPERATURE CONTROL】 Features high-performance, low-noise redundant IMUs from Bosch (BMI055) and InvenSense (ICM-42688-P). Integrated onboard heating resistors provide temperature control, allowing the IMUs to consistently work at optimum temperature for unmatched reliability.
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Use a common-cause analysis to identify what could disable multiple channels at once. Depending on the system, examine:
- Power feeds, power supplies, grounding, and protection devices.
- Clocks, synchronization mechanisms, communication networks, and shared backplanes.
- Shared sensors, actuators, input data, and output paths.
- Location, heat, vibration, moisture, contamination, fire, and other environmental exposures.
- Common software, configuration, requirements, maintenance procedures, and operator actions.
Separation or diversity is useful only when it addresses a credible common cause. Redundant processors that depend on one indispensable network or one shared sensor may not preserve the function the system needs. Conversely, adding independence can increase cost and engineering complexity, so the required level should follow the hazard and availability needs rather than the appeal of a particular architecture.
Design the failover around the system’s required behavior
- Define the target. State the hazard, acceptable failure probability, availability target, restoration time, and failure or operator-error cases the system must tolerate.
- Classify the required response. Decide whether the system must fail safe, remain fail-operational, or degrade gracefully. Specify what happens after a detected disagreement, loss of synchronization, or failed takeover.
- Map the critical path. Identify every component required to deliver the function, not only the processors. Azure Well-Architected guidance recommends identifying critical-path components, building redundancy in layers, selecting active-active or active-passive deployment as appropriate, and overprovisioning to cover failure of an individual redundant instance.
- Remove relevant shared dependencies. Separate processors, power, clocks, communications, and environmental exposure where the common-cause analysis shows that sharing would defeat the required fault tolerance.
- Specify detection and response. Define health monitoring, comparison or voting, the fault thresholds and timing, channel isolation, safe-state behavior, failover policy, and conditions for recovery or failback.
- Validate in the operating environment. Test the failure cases below under representative loads, timing, configuration, and environmental conditions. NASA’s requirement for operational-condition verification is especially relevant to safety-critical redundancy.
- Track results over the lifecycle. Record reliability, availability, supportability, recoverability, failover time, and maintenance results using a consistent measurement framework.
How to test failover and common-cause failures
A successful indicator light or controller self-test is not evidence that the process will survive a real fault. Build a fault-injection plan around the specified failure cases, with acceptance criteria for detection, transition time, output behavior, alarms, and recovery. Protect people and equipment during tests, and verify that the observed result matches the required safe or operational state.
- Establish a baseline. Record normal processor health, synchronization, communications, load, output behavior, and recovery procedure before introducing faults.
- Remove the active processor. For active/standby, induce a controlled active-CPU loss. Measure detection and switchover time; confirm the standby has valid state and that outputs and process behavior meet the requirement.
- Break synchronization or inter-processor communications. Confirm that the system detects stale or divergent state and follows the specified policy rather than silently using bad data.
- Exercise power faults. Test loss of each redundant feed or supply separately, then assess shared upstream power dependencies identified in the common-cause analysis.
- Exercise input and output faults. Test sensor, actuator, and output-path faults where safe and applicable. Confirm that redundancy in the processors has not masked a single point of failure elsewhere in the control path.
- Test disagreement and channel isolation. For checked or voted designs, verify comparison coverage, fault detection, the required safe-state or voting response, and isolation of a faulty channel.
- Test recovery and failback. Restore the failed unit and verify resynchronization, return-to-service criteria, alarms, and whether failback is automatic or requires operator action.
- Assess common causes. Review and, where feasible, test shared dependencies and environmental threats that could affect multiple channels at once. A test of one CPU at a time cannot establish tolerance to a common event.
- Document evidence and corrective action. Preserve the configuration, injected fault, measured timings, outputs, alarms, recovery result, and any deviations. Repeat after material changes to hardware, software, configuration, or operating conditions.
How to measure whether redundancy is working
Do not use “redundant” as a proxy for dependability. Distinguish at least four outcomes: reliability (failure behavior over time), availability (whether the function is usable when needed), supportability (whether it can be maintained), and recoverability (how it returns after a fault). Include failover time and maintenance results because a design that detects faults but cannot restore service may miss the operational target.
Best Value
- 【HIGH-PERFORMANCE H7 PROCESSOR】 Equipped with a powerful 32-bit STM32H743 ARM Cortex-M7 core running up to 480MHz, featuring 2MB Flash memory and 1MB RAM. Delivers the massive computing power required for complex autonomous vehicle algorithms, ensuring efficient and productive development work.
- 【DUAL REDUNDANT IMU & TEMPERATURE CONTROL】 Features high-performance, low-noise redundant IMUs from Bosch (BMI055) and InvenSense (ICM-42688-P). Integrated onboard heating resistors provide temperature control, allowing the IMUs to consistently work at optimum temperature for unmatched reliability.
- 【ADVANCED VIBRATION ISOLATION】 Designed based on the Pixhawk FMUv6C open standard, it incorporates a newly engineered integrated vibration isolation system. Effectively filters out high-frequency drone vibration and reduces sensor noise to guarantee precise readings and better overall flight performance.
- 【FLEXIBLE PWM & BROAD FIRMWARE COMPATIBILITY】 Pre-installed with PX4 Autopilot, and supports ArduPilot (requires v4.3+ for M10 GPS). Features a hardware-switchable PWM signal mode between 3.3V and 5V (accessible by opening the casing) to support a wide range of peripheral hardware.
- 【COST-EFFECTIVE & ULTRA-LOW PROFILE】 Offers a cost-effective design with a low-profile form factor (84.8 x 44 x 12.4 mm). Highly versatile for both academic research (professors, students, corporate labs) and commercial autonomous vehicle applications. Available in ultra-light plastic (34.6g) or durable aluminum (59.3g) cases.
IEEE 982-2024 is an active IEEE standard published on 2024-11-01. It provides definitions, sample requirements, equations, and data-collection guidance for reliability, availability, supportability, and recoverability. IEEE C37.120-2021 is an active guide for selecting protection-system redundancy levels for power-system reliability; it was published 2022-02-28 and ANSI approved 2022-04-29. Its stated domain is power-system protection, so it should not be treated as a universal processor architecture prescription.
NASA NPR 8715.3 also identifies a 95% lower-confidence demonstration for failure probability. That is a confidence qualification in the cited NASA context, not a claim that processor redundancy reduces failure probability by 95%, nor a universal target for other systems.
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