Non-volatile memory (NVM) can benefit edge AI in two distinct ways: it can preserve model weights while a device is powered off, and—in compute-in-memory designs—it can bring weights closer to the computation that uses them. The first can support faster, lower-energy wake-ups; the second can reduce data movement. Neither benefit is automatic: results depend on the memory technology, circuit design, workload and system around it.
How does non-volatile memory help edge AI?
Edge AI runs inference near where data is collected, often on devices with tight power, latency and space budgets. Model weights and intermediate data must be available when the device processes an input. NVM stores information without continuous power, unlike volatile memory, which loses its contents when power is removed. That persistence can help with model storage, but it does not by itself make a complete AI system independent of volatile memory or guarantee lower total power consumption.
It can preserve model weights through power-off
If model weights remain in NVM while a device is off, an event-triggered system may be able to wake and process an input without first reloading all those weights from another storage location. TSMC describes short-latency, low-energy wake-up from power-off as a design goal for edge devices in its RRAM memory research. The benefit depends on how the system is built: persistent weights do not mean that every inference operation can run without volatile memory.
It can reduce weight movement during computation
In compute-in-memory (CIM), a memory array participates in operations such as multiply-and-accumulate (MAC), keeping weights close to the computation. This addresses one source of energy use in conventional architectures: moving data between memory and a separate compute unit. The benefit belongs to the specific CIM architecture and workload; ordinary NVM storage does not automatically reduce a device’s overall energy use.
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What have NVM edge-AI prototypes demonstrated?
Published results show what particular designs can achieve, not a universal rating for NVM or commercial edge devices. The measurements below come from separate studies and should not be treated as a head-to-head benchmark.
ReRAM: logic and MAC operations in one prototype
A 2019 Nature Electronics study demonstrated a 1 Mb ReRAM compute-in-memory macro fabricated in a 65 nm CMOS process. In the study’s setup, the macro reported 4.9 ns access time for three-input Boolean logic operations and 14.8 ns MAC computing time, with energy efficiency of 16.95 tera operations per second per watt. Its evaluated MNIST inference reached 98.8% accuracy using the paper’s split binary-input, ternary-weighted model. These figures describe that macro and evaluation—not the performance or accuracy any edge-AI device should expect. Read the 2019 study.
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MRAM: co-designed sensing and secure CIM
In a 2024 report, TSMC described a design-technology-system co-optimization for edge AI that reduced read energy by 27.1% to 45.3%, with minimal inference-accuracy degradation in the studied setting. This is a result for that approach, not a general MRAM product specification. See TSMC’s MRAM study.
A separate 2023 Nature Electronics paper reported a 6.6 Mb CMOS-integrated STT-MRAM compute-in-memory macro with security mechanisms for edge-AI devices. Its capacity and features are evidence of a research design, not proof that all MRAM devices provide the same capabilities. Read the 2023 study.
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How do ReRAM and MRAM compare for edge AI?
The cited examples illustrate different designs and evidence. Their headline metrics were not measured under a common benchmark, so they do not establish a universal winner.
| Evidence | What the cited source reports | How to interpret it |
|---|---|---|
| ReRAM CIM macro, 2019 | 1 Mb, 4.9 ns Boolean-logic access time, 14.8 ns MAC computing time, 16.95 tera operations per second per watt, and 98.8% MNIST inference accuracy in the paper’s model and evaluation. Nature Electronics | A prototype result for a 65 nm CMOS macro and the study’s test setup; not a general product rating. |
| MRAM sensing co-optimization, 2024 | 27.1%–45.3% lower read energy, with minimal inference-accuracy degradation in the studied edge-AI setting. TSMC Research | A reported design-technology-system result; not a general-purpose product specification. |
| STT-MRAM CIM macro, 2023 | 6.6 Mb capacity and security mechanisms. Nature Electronics | A CMOS-integrated research macro; the cited figure does not establish a comparable energy or latency result. |
What should designers evaluate?
Choose against the intended workload, duty cycle, environment and production needs rather than the memory label alone. Relevant factors include:
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- Read and write energy: The cited MRAM energy reduction concerns reads in a particular co-designed system; write behavior may matter for systems that update weights or state often.
- Latency and throughput: Check the operations and measurement conditions behind any latency figure, and whether they match the model’s access pattern.
- Endurance and retention: Confirm write endurance and data retention at the device’s operating temperatures and over its expected service life.
- Density and process integration: Assess the capacity needed and whether the memory can be integrated with the target process and chip design.
- Variability and model accuracy: Device behavior can affect computed results, so validate accuracy using the intended model and operating conditions.
- Security: Determine whether the design’s security mechanisms address the system’s actual threat model; a feature reported for one macro is not inherent to every NVM.
- Production maturity and qualification: Separate research demonstrations from process offerings that are qualified and in production.
How mature are embedded NVM options?
Availability varies by foundry, process and intended application. TSMC says its 22 nm and 16 nm embedded MRAM (eMRAM) have passed AEC-Q100 automotive qualification and are in production. The same official technology page describes 12 nm automotive-grade and 5 nm high-write-speed eMRAM as under development; these are TSMC-specific status claims, not an inventory of the wider market. The page also characterizes its eMRAM as offering high-speed read/write, high endurance, solder-reflow support and high-temperature data retention; those are vendor claims. TSMC’s eNVM technology page (accessed October 4, 2026).
When does NVM make sense for edge AI?
NVM is most relevant when a design benefits from retaining weights through power-off, reducing movement between memory and computation, or both. Persistent storage and CIM are related but separate design choices: a device can use NVM to retain a model without performing inference in the memory array, while CIM specifically integrates memory with computation. Evaluate the intended workload and implementation evidence rather than assuming persistence alone will lower system power.
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