Choose the high-side and low-side MOSFETs by comparing their total losses at your converter’s actual input voltage, output voltage, load, switching frequency, gate-drive conditions and temperature. The part with the lowest RDS(on) is not automatically the most efficient: lower resistance can come with higher gate charge and greater switching and drive losses.
How do I choose MOSFETs for a synchronous buck converter?
Start with the operating conditions and the controller—not a headline resistance value. A useful comparison estimates conduction, switching-transition, gate-drive, output-capacitance and diode-related losses for each FET in its specific switch position. Texas Instruments describes this balance for its TPS53211 application in MOSFET Selection with the TPS53211.
- Define the operating point. Record the input-voltage range, output voltage, load range, inductor ripple current, switching frequency, gate-drive voltage and current, allowable temperature rise, board and package constraints, and cost target.
- Screen for electrical and thermal fit. Check voltage rating, current capability and safe operating conditions with appropriate design margin. Use RDS(on) specified at the gate voltage you will apply, and account for its increase as the device heats. A room-temperature headline value alone is not enough.
- Estimate conduction loss by position. Use duty-weighted RMS current for each FET, including inductor ripple. The high-side and low-side devices conduct over different intervals, so their losses must be evaluated separately.
- Estimate switching and drive losses. Include switching frequency, gate charge, driver source and sink capability, transition timing and gate-drive voltage. Consider output-capacitance energy where it matters in the switching position.
- Include low-side diode behavior. Account for body-diode conduction during dead time and reverse recovery when the opposite switch turns on.
- Compare total loss and implementation fit. Weigh package and source inductance, thermal path, board copper, footprint, cost, availability and EMI constraints. Parallel FETs may lower conduction resistance but add gate charge; check whether the resulting total loss improves.
- Validate the design on its intended board. Check efficiency, switch-node waveform, device temperature and emissions. If datasheet QOSS or QRR values do not support a fair comparison, evaluate candidates on the same board and under the same operating conditions.
How does MOSFET selection affect buck-converter efficiency?
A synchronous buck’s FET losses have competing contributors. Conduction loss depends on current, duty interval and on-resistance; switching transitions and charging the gates cost energy each cycle. Increasing switching frequency makes charge-related drive and transition losses more consequential. The high-side FET controls the input-to-switch-node transition, while the low-side FET carries inductor current during the synchronous interval and can conduct through its body diode during dead time.
Consequently, compare candidates at the intended operating point rather than ranking them by a single datasheet specification. TI’s MOSFET selection article for switch-mode power supplies discusses the balance between conduction and switching losses. It also illustrates that devices with different resistance can have similar total losses under particular conditions; that example does not establish a universal efficiency or cost rule.
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What is the tradeoff between RDS(on) and gate charge?
Reducing RDS(on) can reduce conduction loss, but lower-resistance devices commonly have higher gate charge. More charge takes more drive energy and can increase switching loss, especially as frequency rises. The best candidate is the one that minimizes the combined losses for the design—not necessarily the one with the lowest resistance or the smallest gate charge in isolation.
For the TPS53211 specifically, TI’s December 2022 application note formalizes the balance using a J/K method, with separate expressions for control (high-side) and rectifying (low-side) MOSFETs. Its candidate condition uses RDS(on), QSW, J and K. Apply those expressions only with the note’s controller and assumptions; a different controller or operating point calls for its applicable guidance and a suitable loss model.
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What else should I compare besides resistance and gate charge?
- Output capacitance: Consider QOSS or EOSS for the switching position where output-capacitance behavior contributes to loss.
- Body diode and recovery: Consider low-side body-diode conduction during dead time and QRR behavior when the high-side device turns on.
- Driver compatibility: Check gate-drive voltage, source and sink capability, and the controller’s charge and timing limits.
- Thermal and package details: Account for junction temperature, thermal resistance, board copper and package parasitics—not just nominal current ratings.
- Layout and emissions: Source inductance and loop area can affect ringing and switching behavior. Changing edge speed may reduce ringing or emissions while increasing switching loss.
Datasheet charge figures do not always provide a like-for-like comparison across vendors. Where the figures are inadequate, use comparable measurements in the same converter layout and conditions rather than treating the published values as directly interchangeable.
How do dead time and slew rate affect efficiency?
During dead time, inductor current may flow through the low-side body diode and incur additional loss. Reducing unnecessary diode conduction can help efficiency, but the high-side and low-side MOSFETs must never conduct simultaneously: overlap can cause shoot-through. Use the controller’s dead-time guidance and verify switching waveforms rather than shortening dead time blindly.
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Slowing a switching edge can reduce ringing or emissions, but a slower transition can increase switching loss. TI reports a 21 dBµV conducted-emissions reduction in a particular LM5140-Q1 example in its slew-rate discussion. That result is specific to the reported application and is not a general efficiency improvement or a prediction for another converter.
Which controller limits matter?
Gate-drive capability and timing are properties of the controller and implementation, not universal MOSFET selection rules. For the TPS53211, TI’s December 2022 note specifies a total gate-drive current below 50 mA and a low-side gate-charge limit of 55 nC, and describes a series-resistor remedy for that controller when low-side charge exceeds the stated limit. The same note gives an illustrative combined gate charge of 100 nC at 500 kHz. These figures are TPS53211-specific guidance and example values, not general limits; consult the documentation for the controller in your design.
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Is CSD86330Q3D the right MOSFET for my buck converter?
TI names CSD86330Q3D in its synchronous-buck MOSFET selection discussion, making it a possible search starting point, not a recommendation for a converter with unspecified requirements. Before selecting it, verify the current manufacturer datasheet for voltage rating, RDS(on) at your gate voltage and temperature, charge behavior, package and controller compatibility. Suitability depends on the operating point and board design.
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