When an interrupt occurs, a CPU accepts an eligible request, transfers execution to an architecture-defined handler, preserves the state needed to resume the interrupted program, and returns when interrupt work is complete. The broad pattern is common, but the details—priority, handler selection, saved registers, nesting, and request completion—depend on the processor, interrupt controller, and peripheral.
What happens when an interrupt occurs?
- A source raises a request. A peripheral or another system component signals an event. An interrupt controller may collect, prioritize, mask, or route the request before it reaches a CPU. For example, the Arm Cortex-M7 works with the Nested Vectored Interrupt Controller (NVIC), while some RISC-V platforms use a Platform-Level Interrupt Controller (PLIC) for platform-level sources. Arm Cortex-M7 Technical Reference Manual; RISC-V PLIC specification.
- The processor decides whether to take it. The request must be eligible under the architecture’s enable, priority, and privilege rules. At RISC-V machine level, interrupt-enable and pending bits, current privilege, and delegation settings affect whether an interrupt is taken at that level. RISC-V machine-level ISA.
- Control moves to a handler. The CPU records information needed to manage the event and selects the relevant handler through architecture-defined vector or trap mechanisms. The handler is often called an interrupt service routine (ISR).
- The event is serviced and completed. The handler or controller performs the device-specific work and the required acknowledgement or clear operation. For example, an Arm timer handler can clear the peripheral’s interrupt request; a PLIC gateway uses completion behavior for applicable routed sources. Arm Cortex-M4 Devices Generic User Guide; RISC-V PLIC specification.
- The interrupted program resumes. The processor restores the necessary context and returns to the interrupted flow. Some processors can optimize consecutive exception handling; Cortex-M, for example, supports tail-chaining between pending exceptions. Arm Cortex-M7 Technical Reference Manual.
How do Cortex-M7 and RISC-V differ?
These examples show why the basic flow should not be mistaken for one universal hardware sequence.
| Aspect | Arm Cortex-M7 example | RISC-V example |
|---|---|---|
| Terminology | Interrupt handling is part of exception handling; the processor and NVIC prioritize and handle exceptions. Arm Cortex-M7 Technical Reference Manual. | Interrupts use the trap mechanism alongside synchronous exceptions. Cause state distinguishes an interrupt from an exception. RISC-V machine-level ISA. |
| Handler selection | The exception vector is fetched while processor state is being stacked. Arm Cortex-M7 Technical Reference Manual. | Trap-vector configuration and cause determine the destination or handling path; behavior depends on privilege and vector mode. RISC-V machine-level ISA. |
| Context preservation | The exception mechanism automatically stacks and restores processor state. Arm Cortex-M7 Technical Reference Manual. | Trap control and status registers record trap information, but saving general-purpose registers is a software and ABI concern; implementation details and extensions can vary. RISC-V machine-level ISA. |
| Priority and nesting | The NVIC prioritizes exceptions; Cortex-M supports preemption and tail-chaining. Arm Cortex-M7 Technical Reference Manual. | Enable, pending, privilege, and delegation rules govern delivery. A PLIC does not itself provide preemption or nesting; cores and software handle that behavior. RISC-V machine-level ISA; RISC-V PLIC specification. |
| Request completion | Completion can be peripheral-specific; the Arm guide’s timer example clears the peripheral request. Arm Cortex-M4 Devices Generic User Guide. | Completion is platform- and controller-specific; the PLIC uses gateway completion for applicable sources. RISC-V PLIC specification. |
What does the CPU save, and what must software save?
Resuming the interrupted program requires preserving its execution context, but hardware does not necessarily save every register on every architecture. Cortex-M7 automatically stacks processor state as part of its exception mechanism. In the RISC-V example, trap state is recorded in control and status registers, while the general-register save path depends on software conventions and implementation details. Check the processor manual and toolchain ABI when writing or reviewing a low-level handler; do not assume one architecture’s stack-frame rules apply to another.
Who acknowledges an interrupt?
There is no single universal acknowledgement step performed by the CPU core. A peripheral may require its status bit or request condition to be cleared, while an interrupt controller may have its own claim-and-completion protocol. The handler must follow the relevant peripheral and controller documentation: clearing only one layer may leave a request pending or allow it to be raised again.
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Why can interrupts be delayed or nested?
A request is not necessarily taken as soon as it is raised. It may be masked, disabled, lower priority than current work, or not eligible at the current privilege level. Whether a higher-priority request can interrupt a handler already running—and how that context is preserved—depends on the CPU and controller. Cortex-M’s NVIC supports prioritization and preemption; in the RISC-V PLIC model, preemption and nesting are handled by the core and software rather than provided by the PLIC itself.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What determines interrupt latency?
Interrupt latency is the delay from a request being raised to the start of its handler. There is no reliable single number for “most CPUs”: the result depends on the processor, memory system, implementation, interrupt controller, and configuration. A specific latency claim should therefore name the exact system and conditions measured rather than present a general figure.
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