At HiPEAC 2026 in Kraków, AMD’s Michaela Blott argued that improving AI efficiency requires continuous co-design across algorithms, computer architecture and silicon—not simply applying today’s optimization techniques at larger scale. Her keynote’s central warning was blunt: “Current methods are just too lazy.”
What Michaela Blott said at HiPEAC 2026
Blott’s keynote, reported by EE Times on January 27, 2026, focused on three connected ways to make AI systems more efficient: silicon diversity, model optimization and agile AI software stacks.
She argued that efficiency goals cannot be met by optimizing one layer in isolation. Algorithms influence hardware requirements; hardware capabilities shape viable algorithms; and compilers and other software determine whether the available hardware is used effectively.
“New algorithms are needed to bring AI efficiency in line with human performance and provide sustainable scaling.”
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“Don’t stop optimizing. Explore and co-design architectures with new algorithms, and in tandem with this, design better AI algorithms with better scaling properties.”
These quotations are attributed to Blott by EE Times. No primary transcript or recording was established for independent wording verification.
A three-layer way to think about AI efficiency
The keynote’s argument is best understood as a co-design problem rather than a ranking of competing products. Each layer exposes opportunities—and constraints—for the others.
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| Layer | What to examine | Why isolated optimization can fall short |
|---|---|---|
| Models and algorithms | Model structure, numerical methods, scaling behavior and the amount of computation required. | A mathematically efficient model may still map poorly to a target processor, memory system or compiler. |
| Architecture and silicon | Processor design, accelerator specialization, memory movement and diversity of hardware targets. | New hardware features deliver little value when algorithms and software cannot exploit them. |
| Software and compiler stack | Compilers, programming models, runtime support and the translation of models into hardware operations. | Hardware capability can remain unused when software support is slow, incomplete or too rigid. |
This framework describes where to look for improvements; it does not establish that one layer is inherently more important or that a particular approach is faster.
Why “don’t get lazy” matters in practice
Scaling is not automatically sustainable
Adding more compute can increase capability, but it can also increase energy use, data movement and system complexity. Blott’s call for algorithms with better scaling properties treats efficiency as an ongoing design objective rather than a one-time tuning exercise.
Co-design can reveal options a single team misses
A model designer might reduce operations, while a hardware designer changes the memory path or adds specialized support. A compiler team may then make those changes usable through a better lowering strategy. Considering the three decisions together can expose improvements unavailable to any one layer considered alone.
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- Supports Linux and Windows.
Agility is a technical requirement
AI methods and hardware targets change quickly. An “agile” stack, in the terms reported from the keynote, is one that can adapt models, compilers and runtimes without requiring every change to be treated as a wholly new software project.
The wider HiPEAC 2026 setting
HiPEAC is a European forum covering computer architecture, programming models, compilers and operating systems, with participation from academic researchers and industry. The 2026 conference was held in Kraków, Poland. That setting matters because the efficiency question spans the full computing stack: it is not solely a model-training or chip-manufacturing issue.
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What the PolyMage Labs example shows
The EE Times account also reported that PolyMage Labs’ automatic compiler for AI hardware was selected for Tenstorrent AI platforms to improve software support. This illustrates the software layer’s role: compiler technology can help connect AI programs with specialized accelerator hardware.
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The report does not provide independent performance measurements, procurement terms or evidence that the selection produced a particular speed, energy or cost improvement. It should therefore be treated as an example of industry activity, not as a benchmark or buying recommendation.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to apply the message to an AI project
- Define the real objective. Decide whether the priority is latency, throughput, energy, memory capacity, cost or a combination. “Efficiency” is not a single metric.
- Profile the whole path. Measure model computation, memory traffic, compilation, runtime overhead and data movement on the intended deployment target.
- Change more than one layer when necessary. Consider model or algorithm changes alongside kernel, architecture and compiler changes instead of assuming the current model must remain fixed.
- Validate on the target system. A theoretical reduction in operations does not prove an end-to-end gain until it is implemented and measured under the workload’s actual conditions.
- Keep the stack adaptable. Favor interfaces and tooling that can accommodate new models and accelerator features as they emerge.
What is—and is not—established by the report
- The keynote made a qualitative case for sustained optimization across algorithms, architecture and silicon.
- It identified silicon diversity, model optimization and agile AI stacks as relevant approaches.
- It supplied no named statistic suitable for proving a specific efficiency gain.
- It did not independently validate the performance of the PolyMage Labs compiler selection for Tenstorrent platforms.
The Bottom Line
HiPEAC 2026’s practical lesson is to treat AI efficiency as an ongoing, cross-layer co-design task. Better algorithms, suitable silicon and an adaptable compiler stack must be developed together; optimizing only one layer risks leaving gains elsewhere untouched.
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