A practical Class E amplifier with a loaded output-network Q of about 3–10 often needs external filtering to meet harmonic limits. The switch generates a rich harmonic spectrum; the resonator attenuates it according to its impedance at each harmonic, and the remaining emissions must be removed without upsetting the fundamental-frequency load that makes zero-voltage switching possible. In the cited Q=5 model, the second-harmonic load current is about −19.85 dBc, so an illustrative −60 dBc limit requires roughly 40.15 dB of additional relative rejection at the second harmonic.
The key rule is to design the resonator, matching network and filter as one nonlinear load. A filter that looks excellent between 50-ohm ports can still detune the Class E stage, increase switch stress or reduce efficiency when connected to its real source and load.
What low Q means in a Class E output network
Loaded Q describes the selectivity of the complete output network after the transistor, load transformation and losses are included. It is not the same as the self-Q of an inductor or capacitor. A component may have a high self-Q while the network has a deliberately low loaded Q because it is coupled strongly to the load for wider bandwidth.
The effective Q also includes transistor output capacitance, switch resistance, inductor loss, capacitor ESR and ESL, transformer loss, PCB loss and the transformed load. Practical Class E treatments commonly use a loaded-Q rule of thumb around 3–10, rather than the very high Q assumed by the simplest sinusoidal-load equations. That range is not a formal limit; the correct value depends on frequency, topology, power and bandwidth.
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Deliberately broadband versus simply lossy
A low loaded Q can be an intentional broadband choice. It broadens the resonator response but weakens its rejection of switching harmonics. A physically poor, lossy resonator is different: it dissipates power without delivering the bandwidth or controlled impedance that a deliberate low-Q design provides.
Why a Class E switch produces harmonics
The transistor is operated as a switch, so drain or collector voltage is nonsinusoidal and switch current is pulsed. Fourier components therefore exist at the fundamental and its harmonics. Class E design primarily arranges voltage and current timing—ideally zero-voltage switching and zero-voltage-derivative switching at turn-on. Those conditions reduce switching loss; they do not make the device waveform or the output intrinsically harmonic-free.
The resonant and matching network extracts the fundamental and presents unfavorable impedances at other frequencies. With an optimum ideal waveform, switch-voltage harmonic amplitudes decrease approximately as 1/n², where n is harmonic number. Mistuning and nonideal switching can produce a slower approximate 1/n decline. The harmonic voltage at the device, current in the load network and power delivered beyond the filter are three different quantities.
Foundational Class E analyses by Raab and harmonic-output/load-network work by Sokal and Raab establish this separation. A useful explanatory treatment, published October 23, 2024, is available from All About Circuits.
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Estimating harmonic current
For each harmonic, represent the switch-voltage component as Vn and the output-network impedance as Zn. The current is:
In = Vn / Zn
Normalizing to the fundamental gives:
In/I1 = (Vn/V1) (Z1/Zn)
Convert the result to a level relative to the fundamental with:
Hn = 20 log10|In/I1|
This equation shows why switch-waveform inspection alone is insufficient. A modest voltage harmonic can drive substantial current if the network impedance is favorable at that frequency, while a large switch-node harmonic may deliver little load power when the network rejects it.
Worked Q=5 example
The following values come from the cited idealized Q=5 model. They are an example, not universal measurements. The final column is the extra attenuation, relative to the filter response at the fundamental, needed to reach an illustrative −60 dBc output target.
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| Component | Intrinsic load-current level | Additional relative attenuation for −60 dBc |
|---|---|---|
| Fundamental | 0 dB | 0 dB |
| Second harmonic | −19.85 dB | 40.15 dB |
| Third harmonic | −35.92 dB | 24.08 dB |
| Fourth harmonic | −42.50 dB | 17.50 dB |
| Fifth harmonic | −49.63 dB | 10.37 dB |
The corresponding current ratios are approximately I2/I1=0.1017, I3/I1=0.0160, I4/I1=0.0075 and I5/I1=0.0033. Required filter rejection is calculated as the target level minus the intrinsic level in dB. It is a relative response requirement, not necessarily the filter’s absolute insertion loss.
Why the second harmonic usually controls the design
The second harmonic is often the strongest remaining component and lies close enough to the fundamental that a low-pass filter must make a sharp transition. It can also interact strongly with transistor capacitance, layout inductance and a deliberate harmonic trap. Designing only for the third or fifth harmonic can therefore leave the dominant emission unresolved.
What low Q changes beyond spectral purity
When Q is reduced, harmonic current flows through the load network instead of being rejected by a narrow resonator. The load current is no longer nearly sinusoidal, and the switch voltage/current waveforms depart from the ideal solution. Zero-voltage or zero-voltage-derivative switching may degrade, changing output power, efficiency and device stress.
The external filter is electrically part of the Class E load. Its fundamental input impedance changes the resistance and reactance used by the switch stage; its harmonic impedances alter waveform shaping. Consequently, ideal high-Q equations should be treated as starting estimates, then replaced by nonlinear simulation and measurement with the actual filter attached.
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Choosing a filtering or harmonic-termination architecture
Low-pass filter
A low-pass network is the usual choice when the operating frequency is the lowest band of interest and all higher harmonics must be rejected. It is familiar and easy to specify, but a stringent second-harmonic requirement may demand a high order or a sharp transition. Wide fractional bandwidth makes that transition harder, and parasitic inductance and capacitance can create extra resonances.
Band-pass filter
A band-pass network suits a fixed or narrow frequency range. It can combine impedance transformation with strong out-of-band rejection, but it is more sensitive to tuning and generally unsuitable for wide frequency agility.
Notch or trap network
A tuned second-harmonic trap can address the dominant requirement with fewer components than a high-order low-pass filter. Its notch frequency and impedance are sensitive to tolerance, self-resonance and layout, and it does not solve broadband higher-harmonic compliance by itself. Include the trap in the switch-side impedance model.
Transmission-line harmonic termination
Distributed matching networks can transform the load at the fundamental while presenting selected harmonic impedances. Transmission-line Class E and inverse-Class E approaches demonstrate this combined function; see the institutional records at the White Rose repository and Queen’s University Belfast. Electrical length, substrate loss and frequency dependence must be included.
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Symmetrical or balanced Class E
A symmetrical arrangement can cancel certain harmonics under nominally equal amplitude and phase drive, reducing the external filtering burden. It adds circuitry and drive complexity, and imbalance between devices, paths or loads reduces the cancellation. An institutional record of a 2005 study is available from PolyU.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Bandwidth, efficiency and matching trade-offs
High Q gives stronger selectivity but narrows the response. Low Q broadens the resonator but passes more harmonic current and shifts filtering work to an external network. Distinguish the following bandwidths rather than quoting one number:
- Amplifier output-power bandwidth
- Drain-efficiency bandwidth
- Impedance-match bandwidth
- Harmonic-compliance bandwidth
- Small-signal frequency-response bandwidth
They can differ substantially; a design may maintain output power across a band yet fail harmonic limits at its edges. A published broadband low-Q Class E design illustrates that low Q can be a deliberate bandwidth choice when harmonic suppression is less dominant; it does not imply unlimited broadband operation. See the journal record.
Filtering also has a loss budget. Inductor copper loss, capacitor ESR and dielectric loss, PCB and connector loss, mismatch loss and circulating current can reduce delivered efficiency. Report the metric and measurement plane:
ηD = PRF,out / PDC,infor drain efficiency.PAE = (PRF,out − PRF,in) / PDC,infor power-added efficiency.
“Output” must be identified as the transistor, matching-network, or post-filter port. More filtering can improve useful fundamental power at the load while lowering total efficiency through its own losses.
Co-design checklist for the complete network
- Set the applicable harmonic limit and operating bandwidth; −60 dBc is an illustrative target, not a universal rule.
- Calculate the intrinsic spectrum and network impedance at every relevant harmonic.
- Specify filter attenuation relative to the fundamental response.
- Verify the filter’s fundamental input impedance and harmonic terminations at the Class E port.
- Check load transformation, RF choke and bias-feed interaction, connector and fixture effects.
- Confirm component current, voltage, thermal and self-resonant-frequency ratings.
- Use distributed elements when lumped parts approach their self-resonance or power limits.
Simulation workflow
- Use ideal Class E equations for initial inductance, capacitance, duty cycle, supply voltage and load estimates.
- Add transistor output and nonlinear capacitances, finite on-resistance, finite rise/fall time, gate or base-drive resistance and package inductance.
- Model finite resonator Q and realistic component parasitics.
- Attach the external filter, matching network and actual load.
- Run periodic-steady-state or harmonic-balance analysis.
- Inspect switch voltage, switch current,
VDS × IDoverlap, fundamental and harmonic output power, efficiency, PAE and component stresses. - Sweep frequency, supply voltage, load mismatch, temperature and component tolerances.
- Optimize the complete nonlinear network rather than a standalone 50-ohm filter.
Generic SPICE transient analysis can help with preliminary switching behavior, but RF harmonic-balance or periodic-steady-state analysis is needed when parasitics, frequency-dependent impedances and steady spectra determine the result.
Measurement workflow and common mistakes
- Measure at the load side of the output filter with a calibrated spectrum or vector-signal analyzer.
- Use rated attenuation, filtering and power handling at the measurement port; a directional coupler or calibrated power sensor improves power accuracy.
- Record fundamental and harmonic powers in dBc at center frequency, band edges and expected load extremes.
- Measure drain efficiency separately from post-filter delivered power.
- Check switch-node voltage and current with suitable low-capacitance, high-voltage probes; do not attach a high-capacitance oscilloscope probe without evaluating loading and bandwidth.
- Do not equate a large switch-node harmonic with equal radiated or delivered harmonic power.
- Do not treat Q=5 values as universal; duty cycle, topology, switch capacitance, DC-feed inductance, losses and filter loading change them.
- Do not equate harmonic attenuation with absolute insertion loss.
- Do not ignore load mismatch, component self-resonance or PCB return paths.
- Do not assume a clean spectrum proves zero-voltage switching or safe transistor stress.
- Do not confuse harmonic suppression with linearity for amplitude-modulated or high-PAPR signals.
When another architecture is preferable
Choose higher Q when narrowband operation and maximum intrinsic rejection matter more than bandwidth. Choose low Q with an external filter when coverage, tuning range or load tolerance justify the added filtering. Consider balanced Class E, transmission-line terminations or integrated resonator/filter approaches when component count, size or second-harmonic rejection dominates. Published examples include a VHF design reporting more than 84 dBc second-harmonic rejection, over 6.5 W output and about 70% drain efficiency across 136–174 MHz; those results belong to that particular prototype, not to low-Q Class E generally. See the ELEX paper. An integrated Class E/FBAR filtering example is indexed at IET Research.
Quick Recap
Design checklist
- Define the applicable harmonic limit, measurement plane and operating corners.
- Define power, efficiency and usable bandwidth separately.
- Determine loaded Q, not just component self-Q.
- Calculate intrinsic harmonic current from switch spectrum and network impedance.
- Set relative filter attenuation, starting with the second harmonic.
- Check fundamental and harmonic impedances with the filter connected.
- Include parasitics, mismatch and tolerance in nonlinear simulation.
- Verify switch stress and component ratings.
- Measure output harmonics, efficiency and edge-of-band behavior with calibrated equipment.
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